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x64: Finish migrating brz and brnz to ISLE (#4614)

Browse Source 
https://github.com/bytecodealliance/wasmtime/pull/4614
This commit is contained in:
Trevor Elliott
2022-08-04 12:58:43 -07:00
committed by GitHub
parent ed8908efcf
commit dc8362ceec
6 changed files with 39 additions and 201 deletions
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103
cranelift/codegen/src/isa/x64/inst/emit_tests.rs
View File

@@ -3261,109 +3261,6 @@ fn test_x64_emit() {
"cmpb %r13b, %r14b",
));
// ========================================================
// TestRmiR
insns.push((
Inst::test_rmi_r(OperandSize::Size64, RegMemImm::reg(r15), rdx),
"4C85FA",
"testq %r15, %rdx",
));
insns.push((
Inst::test_rmi_r(
OperandSize::Size64,
RegMemImm::mem(Amode::imm_reg(99, rdi)),
rdx,
),
"48855763",
"testq 99(%rdi), %rdx",
));
insns.push((
Inst::test_rmi_r(OperandSize::Size64, RegMemImm::imm(127), rdx),
"48F7C27F000000",
"testq $127, %rdx",
));
insns.push((
Inst::test_rmi_r(OperandSize::Size64, RegMemImm::imm(76543210), rdx),
"48F7C2EAF48F04",
"testq $76543210, %rdx",
));
//
insns.push((
Inst::test_rmi_r(OperandSize::Size32, RegMemImm::reg(r15), rdx),
"4485FA",
"testl %r15d, %edx",
));
insns.push((
Inst::test_rmi_r(
OperandSize::Size32,
RegMemImm::mem(Amode::imm_reg(99, rdi)),
rdx,
),
"855763",
"testl 99(%rdi), %edx",
));
insns.push((
Inst::test_rmi_r(OperandSize::Size32, RegMemImm::imm(76543210), rdx),
"F7C2EAF48F04",
"testl $76543210, %edx",
));
//
insns.push((
Inst::test_rmi_r(OperandSize::Size16, RegMemImm::reg(r15), rdx),
"664485FA",
"testw %r15w, %dx",
));
insns.push((
Inst::test_rmi_r(
OperandSize::Size16,
RegMemImm::mem(Amode::imm_reg(99, rdi)),
rdx,
),
"66855763",
"testw 99(%rdi), %dx",
));
insns.push((
Inst::test_rmi_r(OperandSize::Size16, RegMemImm::imm(23210), rdx),
"66F7C2AA5A",
"testw $23210, %dx",
));
//
insns.push((
Inst::test_rmi_r(OperandSize::Size8, RegMemImm::reg(r15), rdx),
"4484FA",
"testb %r15b, %dl",
));
insns.push((
Inst::test_rmi_r(
OperandSize::Size8,
RegMemImm::mem(Amode::imm_reg(99, rdi)),
rdx,
),
"845763",
"testb 99(%rdi), %dl",
));
insns.push((
Inst::test_rmi_r(OperandSize::Size8, RegMemImm::imm(70), rdx),
"F6C246",
"testb $70, %dl",
));
// Extra byte-cases (paranoia!) for test_rmi_r for first operand = R
insns.push((
Inst::test_rmi_r(OperandSize::Size8, RegMemImm::reg(rax), rbx),
"84C3",
"testb %al, %bl",
));
insns.push((
Inst::test_rmi_r(OperandSize::Size8, RegMemImm::reg(rcx), rsi),
"4084CE",
"testb %cl, %sil",
));
insns.push((
Inst::test_rmi_r(OperandSize::Size8, RegMemImm::reg(rcx), r10),
"4184CA",
"testb %cl, %r10b",
));
// ========================================================
// SetCC
insns.push((Inst::setcc(CC::O, w_rsi), "400F90C6", "seto %sil"));

20
cranelift/codegen/src/isa/x64/inst/mod.rs
View File

@@ -619,18 +619,6 @@ impl Inst {
}
}
/// Does a comparison of dst & src for operands of size `size`.
pub(crate) fn test_rmi_r(size: OperandSize, src: RegMemImm, dst: Reg) -> Inst {
src.assert_regclass_is(RegClass::Int);
debug_assert_eq!(dst.class(), RegClass::Int);
Inst::CmpRmiR {
size,
src: GprMemImm::new(src).unwrap(),
dst: Gpr::new(dst).unwrap(),
opcode: CmpOpcode::Test,
}
}
pub(crate) fn trap(trap_code: TrapCode) -> Inst {
Inst::Ud2 { trap_code }
}
@@ -729,14 +717,6 @@ impl Inst {
Inst::JmpKnown { dst }
}
pub(crate) fn jmp_cond(cc: CC, taken: MachLabel, not_taken: MachLabel) -> Inst {
Inst::JmpCond {
cc,
taken,
not_taken,
}
}
pub(crate) fn jmp_unknown(target: RegMem) -> Inst {
target.assert_regclass_is(RegClass::Int);
Inst::JmpUnknown { target }