diff --git a/cranelift/codegen/meta/src/isa/x86/encodings.rs b/cranelift/codegen/meta/src/isa/x86/encodings.rs
index f63a15e3ae..dcdc4d0196 100644
--- a/cranelift/codegen/meta/src/isa/x86/encodings.rs
+++ b/cranelift/codegen/meta/src/isa/x86/encodings.rs
@@ -1975,13 +1975,17 @@ pub(crate) fn define<'defs>(
 
     // SIMD logical operations
     for ty in ValueType::all_lane_types().filter(allowed_simd_type) {
-        // band
+        // and
         let band = band.bind(vector(ty, sse_vector_size));
         e.enc_32_64(band, rec_fa.opcodes(&PAND));
 
-        // bor
+        // or
         let bor = bor.bind(vector(ty, sse_vector_size));
-        e.enc_32_64(bor, rec_fa.nonrex().opcodes(&POR));
+        e.enc_32_64(bor, rec_fa.opcodes(&POR));
+
+        // xor
+        let bxor = bxor.bind(vector(ty, sse_vector_size));
+        e.enc_32_64(bxor, rec_fa.opcodes(&PXOR));
     }
 
     // SIMD icmp using PCMPEQ*
diff --git a/cranelift/filetests/filetests/isa/x86/simd-logical-binemit.clif b/cranelift/filetests/filetests/isa/x86/simd-logical-binemit.clif
index 9500175b86..dd0365b016 100644
--- a/cranelift/filetests/filetests/isa/x86/simd-logical-binemit.clif
+++ b/cranelift/filetests/filetests/isa/x86/simd-logical-binemit.clif
@@ -13,3 +13,9 @@ ebb0(v0: b64x2 [%xmm6], v1: b64x2 [%xmm3]):
 [-, %xmm6]  v2 = band v0, v1      ; bin: 66 0f db f3
             return v2
 }
+
+function %bxor_b32x4(b32x4, b32x4) -> b32x4 {
+ebb0(v0: b32x4 [%xmm4], v1: b32x4 [%xmm0]):
+[-, %xmm4]  v2 = bxor v0, v1      ; bin: 66 0f ef e0
+            return v2
+}