x64: handle tests of b1 values correctly (only LSB is defined).
Previously, `select` and `brz`/`brnz` instructions, when given a `b1` boolean argument, would test whether that boolean argument was nonzero, rather than whether its LSB was nonzero. Since our invariant for mapping CLIF state to machine state is that bits beyond the width of a value are undefined, the proper lowering is to test only the LSB. (aarch64 does not have the same issue because its `Extend` pseudoinst already properly handles masking of b1 values when a zero-extend is requested, as it is for select/brz/brnz.) Found by Nathan Ringo on Zulip [1] (thanks!). [1] https://bytecodealliance.zulipchat.com/#narrow/stream/217117-cranelift/topic/bnot.20on.20b1s
This commit is contained in:
Chris Fallin
@@ -397,6 +397,14 @@ impl fmt::Display for UnaryRmROpcode {
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}
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}
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#[derive(Clone, Copy, PartialEq)]
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pub enum CmpOpcode {
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/// CMP instruction: compute `a - b` and set flags from result.
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Cmp,
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/// TEST instruction: compute `a & b` and set flags from result.
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Test,
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}
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pub(crate) enum InstructionSet {
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SSE,
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SSE2,
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@@ -1311,7 +1311,13 @@ pub(crate) fn emit(
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size,
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src: src_e,
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dst: reg_g,
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opcode,
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} => {
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let is_cmp = match opcode {
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CmpOpcode::Cmp => true,
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CmpOpcode::Test => false,
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};
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let mut prefix = LegacyPrefixes::None;
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if *size == 2 {
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prefix = LegacyPrefixes::_66;
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@@ -1342,16 +1348,26 @@ pub(crate) fn emit(
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}
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}
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// Use the swapped operands encoding, to stay consistent with the output of
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// Use the swapped operands encoding for CMP, to stay consistent with the output of
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// gcc/llvm.
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let opcode = if *size == 1 { 0x38 } else { 0x39 };
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let opcode = match (*size, is_cmp) {
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(1, true) => 0x38,
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(_, true) => 0x39,
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(1, false) => 0x84,
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(_, false) => 0x85,
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};
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emit_std_reg_reg(sink, prefix, opcode, 1, *reg_e, *reg_g, rex);
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}
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RegMemImm::Mem { addr } => {
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let addr = &addr.finalize(state, sink);
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// Whereas here we revert to the "normal" G-E ordering.
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let opcode = if *size == 1 { 0x3A } else { 0x3B };
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// Whereas here we revert to the "normal" G-E ordering for CMP.
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let opcode = match (*size, is_cmp) {
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(1, true) => 0x3A,
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(_, true) => 0x3B,
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(1, false) => 0x84,
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(_, false) => 0x85,
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};
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emit_std_reg_mem(sink, state, info, prefix, opcode, 1, *reg_g, addr, rex);
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}
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@@ -1361,16 +1377,25 @@ pub(crate) fn emit(
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let use_imm8 = low8_will_sign_extend_to_32(*simm32);
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// And also here we use the "normal" G-E ordering.
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let opcode = if *size == 1 {
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let opcode = if is_cmp {
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if *size == 1 {
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0x80
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} else if use_imm8 {
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0x83
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} else {
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0x81
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}
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} else {
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if *size == 1 {
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0xF6
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} else {
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0xF7
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}
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};
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let subopcode = if is_cmp { 7 } else { 0 };
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let enc_g = int_reg_enc(*reg_g);
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emit_std_enc_enc(sink, prefix, opcode, 1, 7 /*subopcode*/, enc_g, rex);
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emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, enc_g, rex);
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emit_simm(sink, if use_imm8 { 1 } else { *size }, *simm32);
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}
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}
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@@ -2648,6 +2648,88 @@ fn test_x64_emit() {
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"cmpb %r13b, %r14b",
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));
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// ========================================================
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// TestRmiR
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insns.push((
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Inst::test_rmi_r(8, RegMemImm::reg(r15), rdx),
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"4C85FA",
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"testq %r15, %rdx",
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));
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insns.push((
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Inst::test_rmi_r(8, RegMemImm::mem(Amode::imm_reg(99, rdi)), rdx),
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"48855763",
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"testq 99(%rdi), %rdx",
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));
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insns.push((
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Inst::test_rmi_r(8, RegMemImm::imm(76543210), rdx),
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"48F7C2EAF48F04",
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"testq $76543210, %rdx",
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));
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//
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insns.push((
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Inst::test_rmi_r(4, RegMemImm::reg(r15), rdx),
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"4485FA",
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"testl %r15d, %edx",
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));
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insns.push((
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Inst::test_rmi_r(4, RegMemImm::mem(Amode::imm_reg(99, rdi)), rdx),
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"855763",
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"testl 99(%rdi), %edx",
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));
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insns.push((
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Inst::test_rmi_r(4, RegMemImm::imm(76543210), rdx),
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"F7C2EAF48F04",
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"testl $76543210, %edx",
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));
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//
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insns.push((
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Inst::test_rmi_r(2, RegMemImm::reg(r15), rdx),
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"664485FA",
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"testw %r15w, %dx",
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));
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insns.push((
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Inst::test_rmi_r(2, RegMemImm::mem(Amode::imm_reg(99, rdi)), rdx),
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"66855763",
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"testw 99(%rdi), %dx",
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));
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insns.push((
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Inst::test_rmi_r(2, RegMemImm::imm(23210), rdx),
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"66F7C2AA5A",
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"testw $23210, %dx",
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));
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//
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insns.push((
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Inst::test_rmi_r(1, RegMemImm::reg(r15), rdx),
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"4484FA",
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"testb %r15b, %dl",
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));
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insns.push((
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Inst::test_rmi_r(1, RegMemImm::mem(Amode::imm_reg(99, rdi)), rdx),
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"845763",
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"testb 99(%rdi), %dl",
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));
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insns.push((
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Inst::test_rmi_r(1, RegMemImm::imm(70), rdx),
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"F6C246",
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"testb $70, %dl",
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));
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// Extra byte-cases (paranoia!) for test_rmi_r for first operand = R
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insns.push((
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Inst::test_rmi_r(1, RegMemImm::reg(rax), rbx),
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"84C3",
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"testb %al, %bl",
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));
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insns.push((
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Inst::test_rmi_r(1, RegMemImm::reg(rcx), rsi),
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"4084CE",
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"testb %cl, %sil",
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));
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insns.push((
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Inst::test_rmi_r(1, RegMemImm::reg(rcx), r10),
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"4184CA",
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"testb %cl, %r10b",
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));
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// ========================================================
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// SetCC
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insns.push((Inst::setcc(CC::O, w_rsi), "400F90C6", "seto %sil"));
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@@ -168,9 +168,10 @@ pub enum Inst {
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dst: Writable<Reg>,
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},
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/// Integer comparisons/tests: cmp (b w l q) (reg addr imm) reg.
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/// Integer comparisons/tests: cmp or test (b w l q) (reg addr imm) reg.
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CmpRmiR {
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size: u8, // 1, 2, 4 or 8
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opcode: CmpOpcode,
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src: RegMemImm,
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dst: Reg,
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},
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@@ -913,8 +914,30 @@ impl Inst {
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) -> Inst {
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src.assert_regclass_is(RegClass::I64);
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debug_assert!(size == 8 || size == 4 || size == 2 || size == 1);
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debug_assert!(dst.get_class() == RegClass::I64);
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Inst::CmpRmiR { size, src, dst }
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debug_assert_eq!(dst.get_class(), RegClass::I64);
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Inst::CmpRmiR {
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size,
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src,
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dst,
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opcode: CmpOpcode::Cmp,
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}
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}
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/// Does a comparison of dst & src for operands of size `size`.
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pub(crate) fn test_rmi_r(
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size: u8, // 1, 2, 4 or 8
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src: RegMemImm,
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dst: Reg,
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) -> Inst {
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src.assert_regclass_is(RegClass::I64);
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debug_assert!(size == 8 || size == 4 || size == 2 || size == 1);
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debug_assert_eq!(dst.get_class(), RegClass::I64);
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Inst::CmpRmiR {
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size,
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src,
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dst,
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opcode: CmpOpcode::Test,
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}
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}
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pub(crate) fn trap(trap_code: TrapCode) -> Inst {
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@@ -1597,12 +1620,23 @@ impl PrettyPrint for Inst {
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dst.to_reg().show_rru(mb_rru)
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),
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Inst::CmpRmiR { size, src, dst } => format!(
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Inst::CmpRmiR {
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size,
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src,
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dst,
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opcode,
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} => {
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let op = match opcode {
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CmpOpcode::Cmp => "cmp",
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CmpOpcode::Test => "test",
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};
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format!(
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"{} {}, {}",
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ljustify2("cmp".to_string(), suffix_bwlq(*size)),
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ljustify2(op.to_string(), suffix_bwlq(*size)),
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src.show_rru_sized(mb_rru, *size),
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show_ireg_sized(*dst, mb_rru, *size)
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),
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)
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}
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Inst::Setcc { cc, dst } => format!(
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"{} {}",
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@@ -175,7 +175,7 @@ mod tests {
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_ => panic!("expected unwind information"),
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};
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assert_eq!(format!("{:?}", fde), "FrameDescriptionEntry { address: Constant(4321), length: 23, lsda: None, instructions: [(1, CfaOffset(16)), (1, Offset(Register(6), -16)), (4, CfaRegister(Register(6))), (16, RememberState), (18, RestoreState)] }");
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assert_eq!(format!("{:?}", fde), "FrameDescriptionEntry { address: Constant(4321), length: 22, lsda: None, instructions: [(1, CfaOffset(16)), (1, Offset(Register(6), -16)), (4, CfaRegister(Register(6))), (15, RememberState), (17, RestoreState)] }");
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}
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fn create_multi_return_function(call_conv: CallConv) -> Function {
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@@ -248,12 +248,6 @@ fn non_reg_input_to_sext_imm(input: NonRegInput, input_ty: Type) -> Option<u32>
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})
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}
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fn input_to_sext_imm<C: LowerCtx<I = Inst>>(ctx: &mut C, spec: InsnInput) -> Option<u32> {
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let input = ctx.get_input_as_source_or_const(spec.insn, spec.input);
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let input_ty = ctx.input_ty(spec.insn, spec.input);
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non_reg_input_to_sext_imm(input, input_ty)
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}
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fn input_to_imm<C: LowerCtx<I = Inst>>(ctx: &mut C, spec: InsnInput) -> Option<u64> {
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ctx.get_input_as_source_or_const(spec.insn, spec.input)
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.constant
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@@ -3731,10 +3725,25 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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let cond_code = ctx.data(icmp).cond_code().unwrap();
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CC::from_intcc(cond_code)
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} else {
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// The input is a boolean value, compare it against zero.
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let sel_ty = ctx.input_ty(insn, 0);
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let size = ctx.input_ty(insn, 0).bytes() as u8;
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let test = put_input_in_reg(ctx, flag_input);
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ctx.emit(Inst::cmp_rmi_r(size, RegMemImm::imm(0), test));
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let test_input = if sel_ty == types::B1 {
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// The input is a boolean value; test the LSB for nonzero with:
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// test reg, 1
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RegMemImm::imm(1)
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} else {
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// The input is an integer; test the whole value for
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// nonzero with:
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// test reg, reg
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//
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// (It doesn't make sense to have a boolean wider than
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// one bit here -- which bit would cause us to select an
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// input?)
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assert!(!is_bool_ty(sel_ty));
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RegMemImm::reg(test)
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};
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ctx.emit(Inst::test_rmi_r(size, test_input, test));
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CC::NZ
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};
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@@ -4355,7 +4364,18 @@ impl LowerBackend for X64Backend {
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_ => unreachable!(),
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};
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let size_bytes = src_ty.bytes() as u8;
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ctx.emit(Inst::cmp_rmi_r(size_bytes, RegMemImm::imm(0), src));
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// See case for `Opcode::Select` above re: testing the
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// boolean input.
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let test_input = if src_ty == types::B1 {
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// test src, 1
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RegMemImm::imm(1)
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} else {
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assert!(!is_bool_ty(src_ty));
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// test src, src
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RegMemImm::reg(src)
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};
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ctx.emit(Inst::test_rmi_r(size_bytes, test_input, src));
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ctx.emit(Inst::jmp_cond(cc, taken, not_taken));
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} else {
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unimplemented!("brz/brnz with non-int type {:?}", src_ty);
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73
cranelift/filetests/filetests/isa/x64/b1.clif
Normal file
73
cranelift/filetests/filetests/isa/x64/b1.clif
Normal file
@@ -0,0 +1,73 @@
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test compile
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target x86_64
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feature "experimental_x64"
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function %f0(b1, i32, i32) -> i32 {
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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block0(v0: b1, v1: i32, v2: i32):
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v3 = select.i32 v0, v1, v2
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; nextln: testb $$1, %dil
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; nextln: cmovnzl %esi, %edx
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return v3
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; nextln: movq %rdx, %rax
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; nextln: movq %rbp, %rsp
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; nextln: popq %rbp
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; nextln: ret
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}
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function %f1(b1) -> i32 {
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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block0(v0: b1):
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brnz v0, block1
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jump block2
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; nextln: testb $$1, %dil
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; nextln: jnz label1; j label2
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block1:
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v1 = iconst.i32 1
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return v1
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; check: movl $$1, %eax
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; nextln: movq %rbp, %rsp
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; nextln: popq %rbp
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; nextln: ret
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block2:
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v2 = iconst.i32 2
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return v2
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; check: movl $$2, %eax
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; nextln: movq %rbp, %rsp
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; nextln: popq %rbp
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; nextln: ret
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}
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function %f2(b1) -> i32 {
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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block0(v0: b1):
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brz v0, block1
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jump block2
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; nextln: testb $$1, %dil
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; nextln: jz label1; j label2
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block1:
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v1 = iconst.i32 1
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return v1
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; check: movl $$1, %eax
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; nextln: movq %rbp, %rsp
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; nextln: popq %rbp
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; nextln: ret
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block2:
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v2 = iconst.i32 2
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return v2
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; check: movl $$2, %eax
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; nextln: movq %rbp, %rsp
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; nextln: popq %rbp
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; nextln: ret
|
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}
|
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Reference in New Issue
Block a user