diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit.rs b/cranelift/codegen/src/isa/aarch64/inst/emit.rs
index a03da96f5f..b137ad3017 100644
--- a/cranelift/codegen/src/isa/aarch64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/emit.rs
@@ -607,7 +607,7 @@ impl<O: MachSectionOutput> MachInstEmit<O> for Inst {
 
                 if let Some(srcloc) = srcloc {
                     // Register the offset at which the actual load instruction starts.
-                    sink.add_trap(srcloc, TrapCode::OutOfBounds);
+                    sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
                 }
 
                 match &mem {
@@ -741,7 +741,7 @@ impl<O: MachSectionOutput> MachInstEmit<O> for Inst {
 
                 if let Some(srcloc) = srcloc {
                     // Register the offset at which the actual load instruction starts.
-                    sink.add_trap(srcloc, TrapCode::OutOfBounds);
+                    sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
                 }
 
                 match &mem {