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Adjust prologue/epilogue generation to work with 32-bit Intel arch.

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Tyler McMullen
2017-11-30 18:50:56 -08:00
committed by Jakob Stoklund Olesen
parent e6481bb4eb
commit daa7a21d05
2 changed files with 33 additions and 15 deletions
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11
lib/cretonne/src/isa/intel/abi.rs
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@@ -15,9 +15,6 @@ static ARG_GPRS: [RU; 6] = [RU::rdi, RU::rsi, RU::rdx, RU::rcx, RU::r8, RU::r9];
/// Return value registers.
static RET_GPRS: [RU; 3] = [RU::rax, RU::rdx, RU::rcx];
/// Callee-saved registers
pub static CSR_GPRS: [RU; 5] = [RU::rbx, RU::r12, RU::r13, RU::r14, RU::r15];
struct Args {
pointer_bytes: u32,
pointer_bits: u16,
@@ -156,3 +153,11 @@ pub fn allocatable_registers(
regs
}
pub fn callee_saved_registers(flags: &shared_settings::Flags) -> Vec<RU> {
if flags.is_64bit() {
return vec![RU::rbx, RU::r12, RU::r13, RU::r14, RU::r15];
} else {
return vec![RU::rbx, RU::rsi, RU::rdi];
}
}