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cranelift-codegen: port bnot lowering to ISLE in x64

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This commit is contained in:
Nick Fitzgerald
2021-12-08 16:54:02 -08:00
committed by Andrew Brown
parent b5e5366550
commit da73952021
5 changed files with 254 additions and 181 deletions
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29
cranelift/codegen/src/isa/x64/lower.rs
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@@ -1533,33 +1533,8 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
| Opcode::Imax
| Opcode::Umax
| Opcode::Imin
| Opcode::Umin => implemented_in_isle(ctx),
Opcode::Bnot => {
let ty = ty.unwrap();
if ty.is_vector() {
unreachable!(
"implemented in ISLE: inst = `{}`, type = `{:?}`",
ctx.dfg().display_inst(insn),
ty
);
} else if ty == types::I128 || ty == types::B128 {
let src = put_input_in_regs(ctx, inputs[0]);
let dst = get_output_reg(ctx, outputs[0]);
ctx.emit(Inst::gen_move(dst.regs()[0], src.regs()[0], types::I64));
ctx.emit(Inst::not(OperandSize::Size64, dst.regs()[0]));
ctx.emit(Inst::gen_move(dst.regs()[1], src.regs()[1], types::I64));
ctx.emit(Inst::not(OperandSize::Size64, dst.regs()[1]));
} else if ty.is_bool() {
unimplemented!("bool bnot")
} else {
let src = put_input_in_reg(ctx, inputs[0]);
let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
ctx.emit(Inst::gen_move(dst, src, ty));
ctx.emit(Inst::not(OperandSize::from_ty(ty), dst));
}
}
| Opcode::Umin
| Opcode::Bnot => implemented_in_isle(ctx),
Opcode::Bitselect => {
let ty = ty.unwrap();