s390x: Enable most memory64 tests
* Support full set of ADD LOGICAL / SUBTRACT LOGICAL instructions * Full implementation of IaddIfcout lowering * Enable most memory64 tests (except simd and threads)
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@@ -973,17 +973,37 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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}
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}
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Opcode::IaddIfcout => {
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// This only supports the operands emitted by dynamic_addr.
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let ty = ty.unwrap();
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assert!(ty == types::I32 || ty == types::I64);
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let alu_op = choose_32_64(ty, ALUOp::Add32, ALUOp::Add64);
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// Emit an ADD LOGICAL instruction, which sets the condition code
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// to indicate an (unsigned) carry bit.
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let alu_op = choose_32_64(ty, ALUOp::AddLogical32, ALUOp::AddLogical64);
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let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
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let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
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let imm = input_matches_uimm32(ctx, inputs[1]).unwrap();
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ctx.emit(Inst::gen_move(rd, rn, ty));
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// Note that this will emit AL(G)FI, which sets the condition
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// code to indicate an (unsigned) carry bit.
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ctx.emit(Inst::AluRUImm32 { alu_op, rd, imm });
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if let Some(imm) = input_matches_uimm32(ctx, inputs[1]) {
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ctx.emit(Inst::gen_move(rd, rn, ty));
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ctx.emit(Inst::AluRUImm32 { alu_op, rd, imm });
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} else if let Some(mem) = input_matches_mem(ctx, inputs[1]) {
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ctx.emit(Inst::gen_move(rd, rn, ty));
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ctx.emit(Inst::AluRX { alu_op, rd, mem });
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} else if let Some(mem) = input_matches_uext32_mem(ctx, inputs[1]) {
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ctx.emit(Inst::gen_move(rd, rn, ty));
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ctx.emit(Inst::AluRX {
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alu_op: ALUOp::AddLogical64Ext32,
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rd,
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mem,
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});
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} else if let Some(rm) = input_matches_uext32_reg(ctx, inputs[1]) {
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ctx.emit(Inst::gen_move(rd, rn, ty));
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ctx.emit(Inst::AluRR {
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alu_op: ALUOp::AddLogical64Ext32,
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rd,
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rm,
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});
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} else {
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let rm = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
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ctx.emit(Inst::AluRRR { alu_op, rd, rn, rm });
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}
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}
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Opcode::UaddSat | Opcode::SaddSat => unimplemented!(),
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