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s390x: Enable most memory64 tests

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* Support full set of ADD LOGICAL / SUBTRACT LOGICAL instructions

* Full implementation of IaddIfcout lowering

* Enable most memory64 tests (except simd and threads)
This commit is contained in:
Ulrich Weigand
2021-09-30 18:36:39 +02:00
parent 937b319e2d
commit d9e6902b69
7 changed files with 569 additions and 88 deletions
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32
cranelift/codegen/src/isa/s390x/inst/mod.rs
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@@ -55,11 +55,17 @@ pub enum ALUOp {
Add64,
Add64Ext16,
Add64Ext32,
AddLogical32,
AddLogical64,
AddLogical64Ext32,
Sub32,
Sub32Ext16,
Sub64,
Sub64Ext16,
Sub64Ext32,
SubLogical32,
SubLogical64,
SubLogical64Ext32,
Mul32,
Mul32Ext16,
Mul64,
@@ -2572,8 +2578,12 @@ impl Inst {
let (op, have_rr) = match alu_op {
ALUOp::Add32 => ("ark", true),
ALUOp::Add64 => ("agrk", true),
ALUOp::AddLogical32 => ("alrk", true),
ALUOp::AddLogical64 => ("algrk", true),
ALUOp::Sub32 => ("srk", true),
ALUOp::Sub64 => ("sgrk", true),
ALUOp::SubLogical32 => ("slrk", true),
ALUOp::SubLogical64 => ("slgrk", true),
ALUOp::Mul32 => ("msrkc", true),
ALUOp::Mul64 => ("msgrkc", true),
ALUOp::And32 => ("nrk", true),
@@ -2623,9 +2633,15 @@ impl Inst {
ALUOp::Add32 => "ar",
ALUOp::Add64 => "agr",
ALUOp::Add64Ext32 => "agfr",
ALUOp::AddLogical32 => "alr",
ALUOp::AddLogical64 => "algr",
ALUOp::AddLogical64Ext32 => "algfr",
ALUOp::Sub32 => "sr",
ALUOp::Sub64 => "sgr",
ALUOp::Sub64Ext32 => "sgfr",
ALUOp::SubLogical32 => "slr",
ALUOp::SubLogical64 => "slgr",
ALUOp::SubLogical64Ext32 => "slgfr",
ALUOp::Mul32 => "msr",
ALUOp::Mul64 => "msgr",
ALUOp::Mul64Ext32 => "msgfr",
@@ -2652,11 +2668,17 @@ impl Inst {
ALUOp::Add64 => (None, Some("ag")),
ALUOp::Add64Ext16 => (None, Some("agh")),
ALUOp::Add64Ext32 => (None, Some("agf")),
ALUOp::AddLogical32 => (Some("al"), Some("aly")),
ALUOp::AddLogical64 => (None, Some("alg")),
ALUOp::AddLogical64Ext32 => (None, Some("algf")),
ALUOp::Sub32 => (Some("s"), Some("sy")),
ALUOp::Sub32Ext16 => (Some("sh"), Some("shy")),
ALUOp::Sub64 => (None, Some("sg")),
ALUOp::Sub64Ext16 => (None, Some("sgh")),
ALUOp::Sub64Ext32 => (None, Some("sgf")),
ALUOp::SubLogical32 => (Some("sl"), Some("sly")),
ALUOp::SubLogical64 => (None, Some("slg")),
ALUOp::SubLogical64Ext32 => (None, Some("slgf")),
ALUOp::Mul32 => (Some("ms"), Some("msy")),
ALUOp::Mul32Ext16 => (Some("mh"), Some("mhy")),
ALUOp::Mul64 => (None, Some("msg")),
@@ -2715,10 +2737,10 @@ impl Inst {
}
&Inst::AluRUImm32 { alu_op, rd, imm } => {
let op = match alu_op {
ALUOp::Add32 => "alfi",
ALUOp::Add64 => "algfi",
ALUOp::Sub32 => "slfi",
ALUOp::Sub64 => "slgfi",
ALUOp::AddLogical32 => "alfi",
ALUOp::AddLogical64 => "algfi",
ALUOp::SubLogical32 => "slfi",
ALUOp::SubLogical64 => "slgfi",
_ => unreachable!(),
};
let rd = rd.to_reg().show_rru(mb_rru);
@@ -2967,6 +2989,8 @@ impl Inst {
let op = match alu_op {
ALUOp::Add32 => "laa",
ALUOp::Add64 => "laag",
ALUOp::AddLogical32 => "laal",
ALUOp::AddLogical64 => "laalg",
ALUOp::And32 => "lan",
ALUOp::And64 => "lang",
ALUOp::Orr32 => "lao",