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s390x: Enable most memory64 tests

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* Support full set of ADD LOGICAL / SUBTRACT LOGICAL instructions

* Full implementation of IaddIfcout lowering

* Enable most memory64 tests (except simd and threads)
This commit is contained in:
Ulrich Weigand
2021-09-30 18:36:39 +02:00
parent 937b319e2d
commit d9e6902b69
7 changed files with 569 additions and 88 deletions
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342
cranelift/codegen/src/isa/s390x/inst/emit_tests.rs
View File

@@ -32,6 +32,26 @@ fn test_s390x_binemit() {
"B9E86045",
"agrk %r4, %r5, %r6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::AddLogical32,
rd: writable_gpr(1),
rn: gpr(2),
rm: gpr(3),
},
"B9FA3012",
"alrk %r1, %r2, %r3",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::AddLogical64,
rd: writable_gpr(4),
rn: gpr(5),
rm: gpr(6),
},
"B9EA6045",
"algrk %r4, %r5, %r6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Sub32,
@@ -52,6 +72,26 @@ fn test_s390x_binemit() {
"B9E96045",
"sgrk %r4, %r5, %r6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::SubLogical32,
rd: writable_gpr(1),
rn: gpr(2),
rm: gpr(3),
},
"B9FB3012",
"slrk %r1, %r2, %r3",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::SubLogical64,
rd: writable_gpr(4),
rn: gpr(5),
rm: gpr(6),
},
"B9EB6045",
"slgrk %r4, %r5, %r6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Mul32,
@@ -261,6 +301,33 @@ fn test_s390x_binemit() {
"B9180045",
"agfr %r4, %r5",
));
insns.push((
Inst::AluRR {
alu_op: ALUOp::AddLogical32,
rd: writable_gpr(1),
rm: gpr(2),
},
"1E12",
"alr %r1, %r2",
));
insns.push((
Inst::AluRR {
alu_op: ALUOp::AddLogical64,
rd: writable_gpr(4),
rm: gpr(5),
},
"B90A0045",
"algr %r4, %r5",
));
insns.push((
Inst::AluRR {
alu_op: ALUOp::AddLogical64Ext32,
rd: writable_gpr(4),
rm: gpr(5),
},
"B91A0045",
"algfr %r4, %r5",
));
insns.push((
Inst::AluRR {
alu_op: ALUOp::Sub32,
@@ -288,6 +355,33 @@ fn test_s390x_binemit() {
"B9190045",
"sgfr %r4, %r5",
));
insns.push((
Inst::AluRR {
alu_op: ALUOp::SubLogical32,
rd: writable_gpr(1),
rm: gpr(2),
},
"1F12",
"slr %r1, %r2",
));
insns.push((
Inst::AluRR {
alu_op: ALUOp::SubLogical64,
rd: writable_gpr(4),
rm: gpr(5),
},
"B90B0045",
"slgr %r4, %r5",
));
insns.push((
Inst::AluRR {
alu_op: ALUOp::SubLogical64Ext32,
rd: writable_gpr(4),
rm: gpr(5),
},
"B91B0045",
"slgfr %r4, %r5",
));
insns.push((
Inst::AluRR {
alu_op: ALUOp::Mul32,
@@ -468,6 +562,62 @@ fn test_s390x_binemit() {
"E31020000018",
"agf %r1, 0(%r2)",
));
insns.push((
Inst::AluRX {
alu_op: ALUOp::AddLogical32,
rd: writable_gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
disp: UImm12::zero(),
flags: MemFlags::trusted(),
},
},
"5E102000",
"al %r1, 0(%r2)",
));
insns.push((
Inst::AluRX {
alu_op: ALUOp::AddLogical32,
rd: writable_gpr(1),
mem: MemArg::BXD20 {
base: gpr(2),
index: zero_reg(),
disp: SImm20::zero(),
flags: MemFlags::trusted(),
},
},
"E3102000005E",
"aly %r1, 0(%r2)",
));
insns.push((
Inst::AluRX {
alu_op: ALUOp::AddLogical64,
rd: writable_gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
disp: UImm12::zero(),
flags: MemFlags::trusted(),
},
},
"E3102000000A",
"alg %r1, 0(%r2)",
));
insns.push((
Inst::AluRX {
alu_op: ALUOp::AddLogical64Ext32,
rd: writable_gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
disp: UImm12::zero(),
flags: MemFlags::trusted(),
},
},
"E3102000001A",
"algf %r1, 0(%r2)",
));
insns.push((
Inst::AluRX {
alu_op: ALUOp::Sub32,
@@ -566,6 +716,62 @@ fn test_s390x_binemit() {
"E31020000019",
"sgf %r1, 0(%r2)",
));
insns.push((
Inst::AluRX {
alu_op: ALUOp::SubLogical32,
rd: writable_gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
disp: UImm12::zero(),
flags: MemFlags::trusted(),
},
},
"5F102000",
"sl %r1, 0(%r2)",
));
insns.push((
Inst::AluRX {
alu_op: ALUOp::SubLogical32,
rd: writable_gpr(1),
mem: MemArg::BXD20 {
base: gpr(2),
index: zero_reg(),
disp: SImm20::zero(),
flags: MemFlags::trusted(),
},
},
"E3102000005F",
"sly %r1, 0(%r2)",
));
insns.push((
Inst::AluRX {
alu_op: ALUOp::SubLogical64,
rd: writable_gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
disp: UImm12::zero(),
flags: MemFlags::trusted(),
},
},
"E3102000000B",
"slg %r1, 0(%r2)",
));
insns.push((
Inst::AluRX {
alu_op: ALUOp::SubLogical64Ext32,
rd: writable_gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
disp: UImm12::zero(),
flags: MemFlags::trusted(),
},
},
"E3102000001B",
"slgf %r1, 0(%r2)",
));
insns.push((
Inst::AluRX {
alu_op: ALUOp::Mul32,
@@ -939,7 +1145,7 @@ fn test_s390x_binemit() {
insns.push((
Inst::AluRUImm32 {
alu_op: ALUOp::Add32,
alu_op: ALUOp::AddLogical32,
rd: writable_gpr(7),
imm: 0,
},
@@ -948,7 +1154,7 @@ fn test_s390x_binemit() {
));
insns.push((
Inst::AluRUImm32 {
alu_op: ALUOp::Add32,
alu_op: ALUOp::AddLogical32,
rd: writable_gpr(7),
imm: 4294967295,
},
@@ -957,7 +1163,7 @@ fn test_s390x_binemit() {
));
insns.push((
Inst::AluRUImm32 {
alu_op: ALUOp::Sub32,
alu_op: ALUOp::SubLogical32,
rd: writable_gpr(7),
imm: 0,
},
@@ -966,7 +1172,7 @@ fn test_s390x_binemit() {
));
insns.push((
Inst::AluRUImm32 {
alu_op: ALUOp::Sub32,
alu_op: ALUOp::SubLogical32,
rd: writable_gpr(7),
imm: 4294967295,
},
@@ -975,7 +1181,7 @@ fn test_s390x_binemit() {
));
insns.push((
Inst::AluRUImm32 {
alu_op: ALUOp::Add64,
alu_op: ALUOp::AddLogical64,
rd: writable_gpr(7),
imm: 0,
},
@@ -984,7 +1190,7 @@ fn test_s390x_binemit() {
));
insns.push((
Inst::AluRUImm32 {
alu_op: ALUOp::Add64,
alu_op: ALUOp::AddLogical64,
rd: writable_gpr(7),
imm: 4294967295,
},
@@ -993,7 +1199,7 @@ fn test_s390x_binemit() {
));
insns.push((
Inst::AluRUImm32 {
alu_op: ALUOp::Sub64,
alu_op: ALUOp::SubLogical64,
rd: writable_gpr(7),
imm: 0,
},
@@ -1002,7 +1208,7 @@ fn test_s390x_binemit() {
));
insns.push((
Inst::AluRUImm32 {
alu_op: ALUOp::Sub64,
alu_op: ALUOp::SubLogical64,
rd: writable_gpr(7),
imm: 4294967295,
},
@@ -2325,6 +2531,126 @@ fn test_s390x_binemit() {
"EB456FFF7FE8",
"laag %r4, %r5, 524287(%r6)",
));
insns.push((
Inst::AtomicRmw {
alu_op: ALUOp::AddLogical32,
rd: writable_gpr(4),
rn: gpr(5),
mem: MemArg::BXD20 {
base: zero_reg(),
index: zero_reg(),
disp: SImm20::maybe_from_i64(-524288).unwrap(),
flags: MemFlags::trusted(),
},
},
"EB45000080FA",
"laal %r4, %r5, -524288",
));
insns.push((
Inst::AtomicRmw {
alu_op: ALUOp::AddLogical32,
rd: writable_gpr(4),
rn: gpr(5),
mem: MemArg::BXD20 {
base: zero_reg(),
index: zero_reg(),
disp: SImm20::maybe_from_i64(524287).unwrap(),
flags: MemFlags::trusted(),
},
},
"EB450FFF7FFA",
"laal %r4, %r5, 524287",
));
insns.push((
Inst::AtomicRmw {
alu_op: ALUOp::AddLogical32,
rd: writable_gpr(4),
rn: gpr(5),
mem: MemArg::BXD20 {
base: gpr(6),
index: zero_reg(),
disp: SImm20::maybe_from_i64(-524288).unwrap(),
flags: MemFlags::trusted(),
},
},
"EB45600080FA",
"laal %r4, %r5, -524288(%r6)",
));
insns.push((
Inst::AtomicRmw {
alu_op: ALUOp::AddLogical32,
rd: writable_gpr(4),
rn: gpr(5),
mem: MemArg::BXD20 {
base: gpr(6),
index: zero_reg(),
disp: SImm20::maybe_from_i64(524287).unwrap(),
flags: MemFlags::trusted(),
},
},
"EB456FFF7FFA",
"laal %r4, %r5, 524287(%r6)",
));
insns.push((
Inst::AtomicRmw {
alu_op: ALUOp::AddLogical64,
rd: writable_gpr(4),
rn: gpr(5),
mem: MemArg::BXD20 {
base: zero_reg(),
index: zero_reg(),
disp: SImm20::maybe_from_i64(-524288).unwrap(),
flags: MemFlags::trusted(),
},
},
"EB45000080EA",
"laalg %r4, %r5, -524288",
));
insns.push((
Inst::AtomicRmw {
alu_op: ALUOp::AddLogical64,
rd: writable_gpr(4),
rn: gpr(5),
mem: MemArg::BXD20 {
base: zero_reg(),
index: zero_reg(),
disp: SImm20::maybe_from_i64(524287).unwrap(),
flags: MemFlags::trusted(),
},
},
"EB450FFF7FEA",
"laalg %r4, %r5, 524287",
));
insns.push((
Inst::AtomicRmw {
alu_op: ALUOp::AddLogical64,
rd: writable_gpr(4),
rn: gpr(5),
mem: MemArg::BXD20 {
base: gpr(6),
index: zero_reg(),
disp: SImm20::maybe_from_i64(-524288).unwrap(),
flags: MemFlags::trusted(),
},
},
"EB45600080EA",
"laalg %r4, %r5, -524288(%r6)",
));
insns.push((
Inst::AtomicRmw {
alu_op: ALUOp::AddLogical64,
rd: writable_gpr(4),
rn: gpr(5),
mem: MemArg::BXD20 {
base: gpr(6),
index: zero_reg(),
disp: SImm20::maybe_from_i64(524287).unwrap(),
flags: MemFlags::trusted(),
},
},
"EB456FFF7FEA",
"laalg %r4, %r5, 524287(%r6)",
));
insns.push((
Inst::AtomicRmw {
alu_op: ALUOp::And32,