s390x: Enable most memory64 tests
* Support full set of ADD LOGICAL / SUBTRACT LOGICAL instructions * Full implementation of IaddIfcout lowering * Enable most memory64 tests (except simd and threads)
This commit is contained in:
Ulrich Weigand
@@ -956,24 +956,28 @@ impl MachInstEmit for Inst {
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match self {
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&Inst::AluRRR { alu_op, rd, rn, rm } => {
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let (opcode, have_rr) = match alu_op {
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ALUOp::Add32 => (0xb9f8, true), // ARK
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ALUOp::Add64 => (0xb9e8, true), // AGRK
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ALUOp::Sub32 => (0xb9f9, true), // SRK
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ALUOp::Sub64 => (0xb9e9, true), // SGRK
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ALUOp::Mul32 => (0xb9fd, true), // MSRKC
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ALUOp::Mul64 => (0xb9ed, true), // MSGRKC
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ALUOp::And32 => (0xb9f4, true), // NRK
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ALUOp::And64 => (0xb9e4, true), // NGRK
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ALUOp::Orr32 => (0xb9f6, true), // ORK
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ALUOp::Orr64 => (0xb9e6, true), // OGRK
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ALUOp::Xor32 => (0xb9f7, true), // XRK
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ALUOp::Xor64 => (0xb9e7, true), // XGRK
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ALUOp::AndNot32 => (0xb974, false), // NNRK
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ALUOp::AndNot64 => (0xb964, false), // NNGRK
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ALUOp::OrrNot32 => (0xb976, false), // NORK
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ALUOp::OrrNot64 => (0xb966, false), // NOGRK
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ALUOp::XorNot32 => (0xb977, false), // NXRK
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ALUOp::XorNot64 => (0xb967, false), // NXGRK
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ALUOp::Add32 => (0xb9f8, true), // ARK
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ALUOp::Add64 => (0xb9e8, true), // AGRK
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ALUOp::AddLogical32 => (0xb9fa, true), // ALRK
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ALUOp::AddLogical64 => (0xb9ea, true), // ALGRK
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ALUOp::Sub32 => (0xb9f9, true), // SRK
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ALUOp::Sub64 => (0xb9e9, true), // SGRK
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ALUOp::SubLogical32 => (0xb9fb, true), // SLRK
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ALUOp::SubLogical64 => (0xb9eb, true), // SLGRK
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ALUOp::Mul32 => (0xb9fd, true), // MSRKC
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ALUOp::Mul64 => (0xb9ed, true), // MSGRKC
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ALUOp::And32 => (0xb9f4, true), // NRK
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ALUOp::And64 => (0xb9e4, true), // NGRK
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ALUOp::Orr32 => (0xb9f6, true), // ORK
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ALUOp::Orr64 => (0xb9e6, true), // OGRK
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ALUOp::Xor32 => (0xb9f7, true), // XRK
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ALUOp::Xor64 => (0xb9e7, true), // XGRK
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ALUOp::AndNot32 => (0xb974, false), // NNRK
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ALUOp::AndNot64 => (0xb964, false), // NNGRK
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ALUOp::OrrNot32 => (0xb976, false), // NORK
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ALUOp::OrrNot64 => (0xb966, false), // NOGRK
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ALUOp::XorNot32 => (0xb977, false), // NXRK
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ALUOp::XorNot64 => (0xb967, false), // NXGRK
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_ => unreachable!(),
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};
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if have_rr && rd.to_reg() == rn {
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@@ -1003,21 +1007,27 @@ impl MachInstEmit for Inst {
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}
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&Inst::AluRR { alu_op, rd, rm } => {
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let (opcode, is_rre) = match alu_op {
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ALUOp::Add32 => (0x1a, false), // AR
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ALUOp::Add64 => (0xb908, true), // AGR
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ALUOp::Add64Ext32 => (0xb918, true), // AGFR
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ALUOp::Sub32 => (0x1b, false), // SR
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ALUOp::Sub64 => (0xb909, true), // SGR
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ALUOp::Sub64Ext32 => (0xb919, true), // SGFR
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ALUOp::Mul32 => (0xb252, true), // MSR
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ALUOp::Mul64 => (0xb90c, true), // MSGR
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ALUOp::Mul64Ext32 => (0xb91c, true), // MSGFR
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ALUOp::And32 => (0x14, false), // NR
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ALUOp::And64 => (0xb980, true), // NGR
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ALUOp::Orr32 => (0x16, false), // OR
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ALUOp::Orr64 => (0xb981, true), // OGR
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ALUOp::Xor32 => (0x17, false), // XR
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ALUOp::Xor64 => (0xb982, true), // XGR
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ALUOp::Add32 => (0x1a, false), // AR
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ALUOp::Add64 => (0xb908, true), // AGR
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ALUOp::Add64Ext32 => (0xb918, true), // AGFR
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ALUOp::AddLogical32 => (0x1e, false), // ALR
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ALUOp::AddLogical64 => (0xb90a, true), // ALGR
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ALUOp::AddLogical64Ext32 => (0xb91a, true), // ALGFR
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ALUOp::Sub32 => (0x1b, false), // SR
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ALUOp::Sub64 => (0xb909, true), // SGR
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ALUOp::Sub64Ext32 => (0xb919, true), // SGFR
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ALUOp::SubLogical32 => (0x1f, false), // SLR
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ALUOp::SubLogical64 => (0xb90b, true), // SLGR
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ALUOp::SubLogical64Ext32 => (0xb91b, true), // SLGFR
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ALUOp::Mul32 => (0xb252, true), // MSR
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ALUOp::Mul64 => (0xb90c, true), // MSGR
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ALUOp::Mul64Ext32 => (0xb91c, true), // MSGFR
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ALUOp::And32 => (0x14, false), // NR
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ALUOp::And64 => (0xb980, true), // NGR
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ALUOp::Orr32 => (0x16, false), // OR
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ALUOp::Orr64 => (0xb981, true), // OGR
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ALUOp::Xor32 => (0x17, false), // XR
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ALUOp::Xor64 => (0xb982, true), // XGR
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_ => unreachable!(),
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};
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if is_rre {
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@@ -1032,27 +1042,33 @@ impl MachInstEmit for Inst {
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ref mem,
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} => {
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let (opcode_rx, opcode_rxy) = match alu_op {
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ALUOp::Add32 => (Some(0x5a), Some(0xe35a)), // A(Y)
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ALUOp::Add32Ext16 => (Some(0x4a), Some(0xe34a)), // AH(Y)
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ALUOp::Add64 => (None, Some(0xe308)), // AG
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ALUOp::Add64Ext16 => (None, Some(0xe338)), // AGH
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ALUOp::Add64Ext32 => (None, Some(0xe318)), // AGF
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ALUOp::Sub32 => (Some(0x5b), Some(0xe35b)), // S(Y)
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ALUOp::Sub32Ext16 => (Some(0x4b), Some(0xe37b)), // SH(Y)
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ALUOp::Sub64 => (None, Some(0xe309)), // SG
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ALUOp::Sub64Ext16 => (None, Some(0xe339)), // SGH
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ALUOp::Sub64Ext32 => (None, Some(0xe319)), // SGF
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ALUOp::Mul32 => (Some(0x71), Some(0xe351)), // MS(Y)
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ALUOp::Mul32Ext16 => (Some(0x4c), Some(0xe37c)), // MH(Y)
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ALUOp::Mul64 => (None, Some(0xe30c)), // MSG
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ALUOp::Mul64Ext16 => (None, Some(0xe33c)), // MSH
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ALUOp::Mul64Ext32 => (None, Some(0xe31c)), // MSGF
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ALUOp::And32 => (Some(0x54), Some(0xe354)), // N(Y)
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ALUOp::And64 => (None, Some(0xe380)), // NG
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ALUOp::Orr32 => (Some(0x56), Some(0xe356)), // O(Y)
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ALUOp::Orr64 => (None, Some(0xe381)), // OG
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ALUOp::Xor32 => (Some(0x57), Some(0xe357)), // X(Y)
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ALUOp::Xor64 => (None, Some(0xe382)), // XG
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ALUOp::Add32 => (Some(0x5a), Some(0xe35a)), // A(Y)
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ALUOp::Add32Ext16 => (Some(0x4a), Some(0xe34a)), // AH(Y)
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ALUOp::Add64 => (None, Some(0xe308)), // AG
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ALUOp::Add64Ext16 => (None, Some(0xe338)), // AGH
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ALUOp::Add64Ext32 => (None, Some(0xe318)), // AGF
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ALUOp::AddLogical32 => (Some(0x5e), Some(0xe35e)), // AL(Y)
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ALUOp::AddLogical64 => (None, Some(0xe30a)), // ALG
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ALUOp::AddLogical64Ext32 => (None, Some(0xe31a)), // ALGF
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ALUOp::Sub32 => (Some(0x5b), Some(0xe35b)), // S(Y)
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ALUOp::Sub32Ext16 => (Some(0x4b), Some(0xe37b)), // SH(Y)
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ALUOp::Sub64 => (None, Some(0xe309)), // SG
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ALUOp::Sub64Ext16 => (None, Some(0xe339)), // SGH
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ALUOp::Sub64Ext32 => (None, Some(0xe319)), // SGF
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ALUOp::SubLogical32 => (Some(0x5f), Some(0xe35f)), // SL(Y)
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ALUOp::SubLogical64 => (None, Some(0xe30b)), // SLG
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ALUOp::SubLogical64Ext32 => (None, Some(0xe31b)), // SLGF
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ALUOp::Mul32 => (Some(0x71), Some(0xe351)), // MS(Y)
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ALUOp::Mul32Ext16 => (Some(0x4c), Some(0xe37c)), // MH(Y)
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ALUOp::Mul64 => (None, Some(0xe30c)), // MSG
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ALUOp::Mul64Ext16 => (None, Some(0xe33c)), // MSH
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ALUOp::Mul64Ext32 => (None, Some(0xe31c)), // MSGF
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ALUOp::And32 => (Some(0x54), Some(0xe354)), // N(Y)
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ALUOp::And64 => (None, Some(0xe380)), // NG
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ALUOp::Orr32 => (Some(0x56), Some(0xe356)), // O(Y)
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ALUOp::Orr64 => (None, Some(0xe381)), // OG
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ALUOp::Xor32 => (Some(0x57), Some(0xe357)), // X(Y)
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ALUOp::Xor64 => (None, Some(0xe382)), // XG
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_ => unreachable!(),
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};
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let rd = rd.to_reg();
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@@ -1082,10 +1098,10 @@ impl MachInstEmit for Inst {
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}
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&Inst::AluRUImm32 { alu_op, rd, imm } => {
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let opcode = match alu_op {
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ALUOp::Add32 => 0xc2b, // ALFI
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ALUOp::Add64 => 0xc2a, // ALGFI
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ALUOp::Sub32 => 0xc25, // SLFI
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ALUOp::Sub64 => 0xc24, // SLGFI
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ALUOp::AddLogical32 => 0xc2b, // ALFI
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ALUOp::AddLogical64 => 0xc2a, // ALGFI
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ALUOp::SubLogical32 => 0xc25, // SLFI
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ALUOp::SubLogical64 => 0xc24, // SLGFI
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_ => unreachable!(),
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};
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put(sink, &enc_ril_a(opcode, rd.to_reg(), imm));
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@@ -1380,14 +1396,16 @@ impl MachInstEmit for Inst {
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ref mem,
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} => {
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let opcode = match alu_op {
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ALUOp::Add32 => 0xebf8, // LAA
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ALUOp::Add64 => 0xebe8, // LAAG
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ALUOp::And32 => 0xebf4, // LAN
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ALUOp::And64 => 0xebe4, // LANG
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ALUOp::Orr32 => 0xebf6, // LAO
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ALUOp::Orr64 => 0xebe6, // LAOG
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ALUOp::Xor32 => 0xebf7, // LAX
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ALUOp::Xor64 => 0xebe7, // LAXG
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ALUOp::Add32 => 0xebf8, // LAA
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ALUOp::Add64 => 0xebe8, // LAAG
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ALUOp::AddLogical32 => 0xebfa, // LAAL
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ALUOp::AddLogical64 => 0xebea, // LAALG
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ALUOp::And32 => 0xebf4, // LAN
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ALUOp::And64 => 0xebe4, // LANG
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ALUOp::Orr32 => 0xebf6, // LAO
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ALUOp::Orr64 => 0xebe6, // LAOG
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ALUOp::Xor32 => 0xebf7, // LAX
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ALUOp::Xor64 => 0xebe7, // LAXG
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_ => unreachable!(),
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};
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