Bump regalloc2 to 0.7.0 (#6237)

* Bump RA2 to 0.7.0

* Certify the RA2 update

* Import the rustc-hash audit

* Updates for regalloc2

prtest:full

* Update tests

cranelift/codegen/src/isa/aarch64/inst/regs.rs

@@ -230,6 +230,7 @@ pub fn create_reg_env(flags: &settings::Flags) -> MachineEnv {
             ],
         ],
         fixed_stack_slots: vec![],
+        scratch_by_class: [None, None],
     };
 
     if !flags.enable_pinned_reg() {

cranelift/codegen/src/isa/riscv64/inst/regs.rs

@@ -182,6 +182,7 @@ pub fn crate_reg_eviroment(_flags: &settings::Flags) -> MachineEnv {
         preferred_regs_by_class,
         non_preferred_regs_by_class,
         fixed_stack_slots: vec![],
+        scratch_by_class: [None, None],
     }
 }
 

cranelift/codegen/src/isa/s390x/inst/regs.rs

@@ -151,6 +151,7 @@ pub fn create_machine_env(_flags: &settings::Flags) -> MachineEnv {
             ],
         ],
         fixed_stack_slots: vec![],
+        scratch_by_class: [None, None],
     }
 }
 

cranelift/codegen/src/isa/x64/inst/regs.rs

@@ -203,6 +203,7 @@ pub(crate) fn create_reg_env_systemv(flags: &settings::Flags) -> MachineEnv {
             vec![],
         ],
         fixed_stack_slots: vec![],
+        scratch_by_class: [None, None],
     };
 
     debug_assert_eq!(r15(), pinned_reg());

cranelift/codegen/src/machinst/vcode.rs

@@ -82,9 +82,6 @@ pub struct VCode<I: VCodeInst> {
     /// Clobbers: a sparse map from instruction indices to clobber masks.
     clobbers: FxHashMap<InsnIndex, PRegSet>,
 
-    /// Move information: for a given InsnIndex, (src, dst) operand pair.
-    is_move: FxHashMap<InsnIndex, (Operand, Operand)>,
-
     /// Source locations for each instruction. (`SourceLoc` is a `u32`, so it is
     /// reasonable to keep one of these per instruction.)
     srclocs: Vec<RelSourceLoc>,
@@ -581,15 +578,6 @@ impl<I: VCodeInst> VCodeBuilder<I> {
                     "the real register {:?} was used as the destination of a move instruction",
                     dst.to_reg()
                 );
-
-                let src = Operand::reg_use(Self::resolve_vreg_alias_impl(vreg_aliases, src.into()));
-                let dst = Operand::reg_def(Self::resolve_vreg_alias_impl(
-                    vreg_aliases,
-                    dst.to_reg().into(),
-                ));
-
-                // Note that regalloc2 requires these in (src, dst) order.
-                self.vcode.is_move.insert(InsnIndex::new(i), (src, dst));
             }
         }
 
@@ -652,7 +640,6 @@ impl<I: VCodeInst> VCode<I> {
             operands: Vec::with_capacity(30 * n_blocks),
             operand_ranges: Vec::with_capacity(10 * n_blocks),
             clobbers: FxHashMap::default(),
-            is_move: FxHashMap::default(),
             srclocs: Vec::with_capacity(10 * n_blocks),
             entry: BlockIndex::new(0),
             block_ranges: Vec::with_capacity(n_blocks),
@@ -931,16 +918,6 @@ impl<I: VCodeInst> VCode<I> {
                             }
                         }
 
-                        if self.insts[iix.index()].is_move().is_some() {
-                            // Skip moves in the pre-regalloc program;
-                            // all of these are incorporated by the
-                            // regalloc into its unified move handling
-                            // and they come out the other end, if
-                            // still needed (not elided), as
-                            // regalloc-inserted moves.
-                            continue;
-                        }
-
                         // Update the srcloc at this point in the buffer.
                         let srcloc = self.srclocs[iix.index()];
                         if cur_srcloc != Some(srcloc) {
@@ -1287,14 +1264,6 @@ impl<I: VCodeInst> RegallocFunction for VCode<I> {
         self.insts[insn.index()].is_safepoint()
     }
 
-    fn is_move(&self, insn: InsnIndex) -> Option<(Operand, Operand)> {
-        let (a, b) = self.is_move.get(&insn)?;
-        Some((
-            self.assert_operand_not_vreg_alias(*a),
-            self.assert_operand_not_vreg_alias(*b),
-        ))
-    }
-
     fn inst_operands(&self, insn: InsnIndex) -> &[Operand] {
         let (start, end) = self.operand_ranges[insn.index()];
         let ret = &self.operands[start as usize..end as usize];