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[AArch64] Port min/max to ISLE (#4374)

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Copyright (c) 2022, Arm Limited.
This commit is contained in:
Sam Parker
2022-07-05 17:16:45 +01:00
committed by GitHub
parent e91f493ff5
commit d9e0e6a6a9
6 changed files with 511 additions and 28 deletions
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144
cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
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@@ -3576,6 +3576,18 @@ fn test_aarch64_binemit() {
"sshl v8.2d, v22.2d, v2.2d",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Umin,
rd: writable_vreg(0),
rn: vreg(11),
rm: vreg(2),
size: VectorSize::Size8x8,
},
"606D222E",
"umin v0.8b, v11.8b, v2.8b",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Umin,
@@ -3588,6 +3600,18 @@ fn test_aarch64_binemit() {
"umin v1.16b, v12.16b, v3.16b",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Umin,
rd: writable_vreg(29),
rn: vreg(19),
rm: vreg(9),
size: VectorSize::Size16x4,
},
"7D6E692E",
"umin v29.4h, v19.4h, v9.4h",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Umin,
@@ -3600,6 +3624,18 @@ fn test_aarch64_binemit() {
"umin v30.8h, v20.8h, v10.8h",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Umin,
rd: writable_vreg(7),
rn: vreg(21),
rm: vreg(20),
size: VectorSize::Size32x2,
},
"A76EB42E",
"umin v7.2s, v21.2s, v20.2s",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Umin,
@@ -3612,6 +3648,18 @@ fn test_aarch64_binemit() {
"umin v8.4s, v22.4s, v21.4s",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Smin,
rd: writable_vreg(2),
rn: vreg(13),
rm: vreg(4),
size: VectorSize::Size8x8,
},
"A26D240E",
"smin v2.8b, v13.8b, v4.8b",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Smin,
@@ -3624,6 +3672,18 @@ fn test_aarch64_binemit() {
"smin v1.16b, v12.16b, v3.16b",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Smin,
rd: writable_vreg(3),
rn: vreg(2),
rm: vreg(1),
size: VectorSize::Size16x4,
},
"436C610E",
"smin v3.4h, v2.4h, v1.4h",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Smin,
@@ -3636,6 +3696,18 @@ fn test_aarch64_binemit() {
"smin v30.8h, v20.8h, v10.8h",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Smin,
rd: writable_vreg(9),
rn: vreg(22),
rm: vreg(20),
size: VectorSize::Size32x2,
},
"C96EB40E",
"smin v9.2s, v22.2s, v20.2s",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Smin,
@@ -3660,6 +3732,30 @@ fn test_aarch64_binemit() {
"umax v6.8b, v9.8b, v8.8b",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Umax,
rd: writable_vreg(5),
rn: vreg(15),
rm: vreg(8),
size: VectorSize::Size8x16,
},
"E565286E",
"umax v5.16b, v15.16b, v8.16b",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Umax,
rd: writable_vreg(12),
rn: vreg(14),
rm: vreg(3),
size: VectorSize::Size16x4,
},
"CC65632E",
"umax v12.4h, v14.4h, v3.4h",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Umax,
@@ -3672,6 +3768,18 @@ fn test_aarch64_binemit() {
"umax v11.8h, v13.8h, v2.8h",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Umax,
rd: writable_vreg(9),
rn: vreg(13),
rm: vreg(15),
size: VectorSize::Size32x2,
},
"A965AF2E",
"umax v9.2s, v13.2s, v15.2s",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Umax,
@@ -3684,6 +3792,18 @@ fn test_aarch64_binemit() {
"umax v8.4s, v12.4s, v14.4s",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Smax,
rd: writable_vreg(7),
rn: vreg(8),
rm: vreg(9),
size: VectorSize::Size8x8,
},
"0765290E",
"smax v7.8b, v8.8b, v9.8b",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Smax,
@@ -3696,6 +3816,18 @@ fn test_aarch64_binemit() {
"smax v6.16b, v9.16b, v8.16b",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Smax,
rd: writable_vreg(11),
rn: vreg(12),
rm: vreg(13),
size: VectorSize::Size16x4,
},
"8B656D0E",
"smax v11.4h, v12.4h, v13.4h",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Smax,
@@ -3708,6 +3840,18 @@ fn test_aarch64_binemit() {
"smax v11.8h, v13.8h, v2.8h",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Smax,
rd: writable_vreg(14),
rn: vreg(16),
rm: vreg(18),
size: VectorSize::Size32x2,
},
"0E66B20E",
"smax v14.2s, v16.2s, v18.2s",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Smax,