lib/codegen-meta moved into lib/codegen. (#423)

* lib/codegen-meta moved into lib/codegen.

* Renamed codegen-meta and existing meta.

lib/codegen/meta-python/isa/arm32/__init__.py

@@ -0,0 +1,15 @@
+"""
+ARM 32-bit Architecture
+-----------------------
+
+This target ISA generates code for ARMv7 and ARMv8 CPUs in 32-bit mode
+(AArch32). We support both ARM and Thumb2 instruction encodings.
+"""
+
+from __future__ import absolute_import
+from . import defs
+from . import settings, registers  # noqa
+from cdsl.isa import TargetISA  # noqa
+
+# Re-export the primary target ISA definition.
+ISA = defs.ISA.finish()  # type: TargetISA

lib/codegen/meta-python/isa/arm32/defs.py

@@ -0,0 +1,19 @@
+"""
+ARM 32-bit definitions.
+
+Commonly used definitions.
+"""
+from __future__ import absolute_import
+from cdsl.isa import TargetISA, CPUMode
+import base.instructions
+from base.legalize import narrow
+
+ISA = TargetISA('arm32', [base.instructions.GROUP])  # type: TargetISA
+
+# CPU modes for 32-bit ARM and Thumb2.
+A32 = CPUMode('A32', ISA)
+T32 = CPUMode('T32', ISA)
+
+# TODO: Refine these.
+A32.legalize_type(narrow)
+T32.legalize_type(narrow)

lib/codegen/meta-python/isa/arm32/registers.py

@@ -0,0 +1,45 @@
+"""
+ARM32 register banks.
+"""
+from __future__ import absolute_import
+from cdsl.registers import RegBank, RegClass
+from .defs import ISA
+
+
+# Define the larger float bank first to avoid the alignment gap.
+FloatRegs = RegBank(
+        'FloatRegs', ISA, r"""
+        Floating point registers.
+
+        The floating point register units correspond to the S-registers, but
+        extended as if there were 64 registers.
+
+        - S registers are one unit each.
+        - D registers are two units each, even D16 and above.
+        - Q registers are 4 units each.
+        """,
+        units=64, prefix='s')
+
+# Special register units:
+# - r15 is the program counter.
+# - r14 is the link register.
+# - r13 is usually the stack pointer.
+IntRegs = RegBank(
+        'IntRegs', ISA,
+        'General purpose registers',
+        units=16, prefix='r')
+
+FlagRegs = RegBank(
+        'FlagRegs', ISA,
+        'Flag registers',
+        units=1,
+        pressure_tracking=False,
+        names=['nzcv'])
+
+GPR = RegClass(IntRegs)
+S = RegClass(FloatRegs, count=32)
+D = RegClass(FloatRegs, width=2)
+Q = RegClass(FloatRegs, width=4)
+FLAG = RegClass(FlagRegs)
+
+RegClass.extract_names(globals())

lib/codegen/meta-python/isa/arm32/settings.py

@@ -0,0 +1,11 @@
+"""
+ARM32 settings.
+"""
+from __future__ import absolute_import
+from cdsl.settings import SettingGroup
+import base.settings as shared
+from .defs import ISA
+
+ISA.settings = SettingGroup('arm32', parent=shared.group)
+
+ISA.settings.close(globals())