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Remove uses of reg_mod from s390x (#5073)

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Remove uses of reg_mod from the s390x backend. This required moving away from using r0/r1 as the result registers from a few different pseudo instructions, standardizing instead on r2/r3. That change was necessary as regalloc2 will not correctly allocate registers that aren't listed in the allocatable set, which r0/r1 are not.

Co-authored-by: Ulrich Weigand <ulrich.weigand@de.ibm.com>
Co-authored-by: Chris Fallin <chris@cfallin.org>
This commit is contained in:
Trevor Elliott
2022-10-21 09:22:16 -07:00
committed by GitHub
parent 204d4c332c
commit d9753fac2b
19 changed files with 1215 additions and 758 deletions
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48
cranelift/filetests/filetests/isa/s390x/conversions.clif
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@@ -8,9 +8,9 @@ block0(v0: i64):
}
; block0:
; vgbm %v4, 0
; vlvgg %v4, %r3, 1
; vst %v4, 0(%r2)
; vgbm %v5, 0
; vlvgg %v5, %r3, 1
; vst %v5, 0(%r2)
; br %r14
function %uextend_i32_i128(i32) -> i128 {
@@ -20,9 +20,9 @@ block0(v0: i32):
}
; block0:
; vgbm %v4, 0
; vlvgf %v4, %r3, 3
; vst %v4, 0(%r2)
; vgbm %v5, 0
; vlvgf %v5, %r3, 3
; vst %v5, 0(%r2)
; br %r14
function %uextend_i32_i64(i32) -> i64 {
@@ -42,9 +42,9 @@ block0(v0: i16):
}
; block0:
; vgbm %v4, 0
; vlvgh %v4, %r3, 7
; vst %v4, 0(%r2)
; vgbm %v5, 0
; vlvgh %v5, %r3, 7
; vst %v5, 0(%r2)
; br %r14
function %uextend_i16_i64(i16) -> i64 {
@@ -74,9 +74,9 @@ block0(v0: i8):
}
; block0:
; vgbm %v4, 0
; vlvgb %v4, %r3, 15
; vst %v4, 0(%r2)
; vgbm %v5, 0
; vlvgb %v5, %r3, 15
; vst %v5, 0(%r2)
; br %r14
function %uextend_i8_i64(i8) -> i64 {
@@ -336,8 +336,8 @@ block0(v0: i128):
; vceqgs %v7, %v0, %v5
; lghi %r3, 0
; locghine %r3, -1
; vlvgp %v20, %r3, %r3
; vst %v20, 0(%r2)
; vlvgp %v21, %r3, %r3
; vst %v21, 0(%r2)
; br %r14
function %bmask_i128_i64(i128) -> i64 {
@@ -406,8 +406,8 @@ block0(v0: i64, v1: i64):
; cghi %r4, 0
; lghi %r4, 0
; locghilh %r4, -1
; vlvgp %v17, %r4, %r4
; vst %v17, 0(%r2)
; vlvgp %v18, %r4, %r4
; vst %v18, 0(%r2)
; br %r14
function %bmask_i64_i64(i64, i64) -> i64 {
@@ -468,8 +468,8 @@ block0(v0: i32, v1: i32):
; chi %r4, 0
; lghi %r4, 0
; locghilh %r4, -1
; vlvgp %v17, %r4, %r4
; vst %v17, 0(%r2)
; vlvgp %v18, %r4, %r4
; vst %v18, 0(%r2)
; br %r14
function %bmask_i32_i64(i32, i32) -> i64 {
@@ -531,8 +531,8 @@ block0(v0: i16, v1: i16):
; chi %r3, 0
; lghi %r3, 0
; locghilh %r3, -1
; vlvgp %v19, %r3, %r3
; vst %v19, 0(%r2)
; vlvgp %v20, %r3, %r3
; vst %v20, 0(%r2)
; br %r14
function %bmask_i16_i64(i16, i16) -> i64 {
@@ -598,8 +598,8 @@ block0(v0: i8, v1: i8):
; chi %r3, 0
; lghi %r3, 0
; locghilh %r3, -1
; vlvgp %v19, %r3, %r3
; vst %v19, 0(%r2)
; vlvgp %v20, %r3, %r3
; vst %v20, 0(%r2)
; br %r14
function %bmask_i8_i64(i8, i8) -> i64 {
@@ -665,8 +665,8 @@ block0(v0: i8, v1: i8):
; chi %r3, 0
; lghi %r3, 0
; locghilh %r3, -1
; vlvgp %v19, %r3, %r3
; vst %v19, 0(%r2)
; vlvgp %v20, %r3, %r3
; vst %v20, 0(%r2)
; br %r14
function %bmask_i8_i64(i8, i8) -> i64 {