ARM64 backend, part 3 / 11: MachInst infrastructure.
This patch adds the MachInst, or Machine Instruction, infrastructure. This is the machine-independent portion of the new backend design. It contains the implementation of the "vcode" (virtual-registerized code) container, the top-level lowering algorithm and compilation pipeline, and the trait definitions that the machine backends will fill in. This backend infrastructure is included in the compilation of the `codegen` crate, but it is not yet tied into the public APIs; that patch will come last, after all the other pieces are filled in. This patch contains code written by Julian Seward <jseward@acm.org> and Benjamin Bouvier <public@benj.me>, originally developed on a side-branch before rebasing and condensing into this patch series. See the `arm64` branch at `https://github.com/cfallin/wasmtime` for original development history. Co-authored-by: Julian Seward <jseward@acm.org> Co-authored-by: Benjamin Bouvier <public@benj.me>
This commit is contained in:
Chris Fallin
723
cranelift/codegen/src/machinst/lower.rs
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723
cranelift/codegen/src/machinst/lower.rs
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@@ -0,0 +1,723 @@
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//! This module implements lowering (instruction selection) from Cranelift IR
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//! to machine instructions with virtual registers. This is *almost* the final
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//! machine code, except for register allocation.
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use crate::binemit::CodeSink;
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use crate::dce::has_side_effect;
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use crate::entity::SecondaryMap;
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use crate::ir::{
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Block, ExternalName, Function, GlobalValueData, Inst, InstructionData, MemFlags, Opcode,
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Signature, SourceLoc, Type, Value, ValueDef,
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};
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use crate::isa::registers::RegUnit;
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use crate::machinst::{
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ABIBody, BlockIndex, MachInst, MachInstEmit, VCode, VCodeBuilder, VCodeInst,
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};
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use crate::num_uses::NumUses;
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use regalloc::Function as RegallocFunction;
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use regalloc::{RealReg, Reg, RegClass, Set, VirtualReg, Writable};
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use alloc::boxed::Box;
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use alloc::vec::Vec;
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use log::debug;
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use smallvec::SmallVec;
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use std::collections::VecDeque;
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use std::ops::Range;
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/// A context that machine-specific lowering code can use to emit lowered instructions. This is the
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/// view of the machine-independent per-function lowering context that is seen by the machine
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/// backend.
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pub trait LowerCtx<I> {
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/// Get the instdata for a given IR instruction.
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fn data(&self, ir_inst: Inst) -> &InstructionData;
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/// Get the controlling type for a polymorphic IR instruction.
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fn ty(&self, ir_inst: Inst) -> Type;
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/// Emit a machine instruction.
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fn emit(&mut self, mach_inst: I);
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/// Indicate that an IR instruction has been merged, and so one of its
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/// uses is gone (replaced by uses of the instruction's inputs). This
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/// helps the lowering algorithm to perform on-the-fly DCE, skipping over
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/// unused instructions (such as immediates incorporated directly).
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fn merged(&mut self, from_inst: Inst);
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/// Get the producing instruction, if any, and output number, for the `idx`th input to the
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/// given IR instruction
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fn input_inst(&self, ir_inst: Inst, idx: usize) -> Option<(Inst, usize)>;
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/// Map a Value to its associated writable (probably virtual) Reg.
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fn value_to_writable_reg(&self, val: Value) -> Writable<Reg>;
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/// Map a Value to its associated (probably virtual) Reg.
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fn value_to_reg(&self, val: Value) -> Reg;
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/// Get the `idx`th input to the given IR instruction as a virtual register.
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fn input(&self, ir_inst: Inst, idx: usize) -> Reg;
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/// Get the `idx`th output of the given IR instruction as a virtual register.
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fn output(&self, ir_inst: Inst, idx: usize) -> Writable<Reg>;
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/// Get the number of inputs to the given IR instruction.
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fn num_inputs(&self, ir_inst: Inst) -> usize;
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/// Get the number of outputs to the given IR instruction.
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fn num_outputs(&self, ir_inst: Inst) -> usize;
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/// Get the type for an instruction's input.
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fn input_ty(&self, ir_inst: Inst, idx: usize) -> Type;
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/// Get the type for an instruction's output.
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fn output_ty(&self, ir_inst: Inst, idx: usize) -> Type;
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/// Get a new temp.
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fn tmp(&mut self, rc: RegClass, ty: Type) -> Writable<Reg>;
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/// Get the number of block params.
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fn num_bb_params(&self, bb: Block) -> usize;
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/// Get the register for a block param.
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fn bb_param(&self, bb: Block, idx: usize) -> Reg;
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/// Get the register for a return value.
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fn retval(&self, idx: usize) -> Writable<Reg>;
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/// Get the target for a call instruction, as an `ExternalName`.
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fn call_target<'b>(&'b self, ir_inst: Inst) -> Option<&'b ExternalName>;
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/// Get the signature for a call or call-indirect instruction.
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fn call_sig<'b>(&'b self, ir_inst: Inst) -> Option<&'b Signature>;
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/// Get the symbol name and offset for a symbol_value instruction.
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fn symbol_value<'b>(&'b self, ir_inst: Inst) -> Option<(&'b ExternalName, i64)>;
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/// Returns the memory flags of a given memory access.
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fn memflags(&self, ir_inst: Inst) -> Option<MemFlags>;
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/// Get the source location for a given instruction.
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fn srcloc(&self, ir_inst: Inst) -> SourceLoc;
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}
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/// A machine backend.
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pub trait LowerBackend {
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/// The machine instruction type.
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type MInst: VCodeInst;
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/// Lower a single instruction. Instructions are lowered in reverse order.
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/// This function need not handle branches; those are always passed to
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/// `lower_branch_group` below.
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fn lower<C: LowerCtx<Self::MInst>>(&self, ctx: &mut C, inst: Inst);
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/// Lower a block-terminating group of branches (which together can be seen as one
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/// N-way branch), given a vcode BlockIndex for each target.
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fn lower_branch_group<C: LowerCtx<Self::MInst>>(
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&self,
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ctx: &mut C,
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insts: &[Inst],
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targets: &[BlockIndex],
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fallthrough: Option<BlockIndex>,
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);
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}
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/// Machine-independent lowering driver / machine-instruction container. Maintains a correspondence
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/// from original Inst to MachInsts.
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pub struct Lower<'a, I: VCodeInst> {
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// The function to lower.
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f: &'a Function,
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// Lowered machine instructions.
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vcode: VCodeBuilder<I>,
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// Number of active uses (minus `dec_use()` calls by backend) of each instruction.
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num_uses: SecondaryMap<Inst, u32>,
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// Mapping from `Value` (SSA value in IR) to virtual register.
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value_regs: SecondaryMap<Value, Reg>,
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// Return-value vregs.
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retval_regs: Vec<Reg>,
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// Next virtual register number to allocate.
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next_vreg: u32,
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}
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fn alloc_vreg(
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value_regs: &mut SecondaryMap<Value, Reg>,
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regclass: RegClass,
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value: Value,
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next_vreg: &mut u32,
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) -> VirtualReg {
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if value_regs[value].get_index() == 0 {
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// default value in map.
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let v = *next_vreg;
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*next_vreg += 1;
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value_regs[value] = Reg::new_virtual(regclass, v);
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}
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value_regs[value].as_virtual_reg().unwrap()
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}
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enum GenerateReturn {
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Yes,
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No,
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}
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impl<'a, I: VCodeInst> Lower<'a, I> {
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/// Prepare a new lowering context for the given IR function.
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pub fn new(f: &'a Function, abi: Box<dyn ABIBody<I>>) -> Lower<'a, I> {
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let mut vcode = VCodeBuilder::new(abi);
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let num_uses = NumUses::compute(f).take_uses();
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let mut next_vreg: u32 = 1;
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// Default register should never be seen, but the `value_regs` map needs a default and we
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// don't want to push `Option` everywhere. All values will be assigned registers by the
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// loops over block parameters and instruction results below.
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//
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// We do not use vreg 0 so that we can detect any unassigned register that leaks through.
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let default_register = Reg::new_virtual(RegClass::I32, 0);
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let mut value_regs = SecondaryMap::with_default(default_register);
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// Assign a vreg to each value.
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for bb in f.layout.blocks() {
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for param in f.dfg.block_params(bb) {
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let vreg = alloc_vreg(
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&mut value_regs,
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I::rc_for_type(f.dfg.value_type(*param)),
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*param,
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&mut next_vreg,
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);
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vcode.set_vreg_type(vreg, f.dfg.value_type(*param));
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}
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for inst in f.layout.block_insts(bb) {
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for result in f.dfg.inst_results(inst) {
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let vreg = alloc_vreg(
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&mut value_regs,
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I::rc_for_type(f.dfg.value_type(*result)),
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*result,
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&mut next_vreg,
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);
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vcode.set_vreg_type(vreg, f.dfg.value_type(*result));
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}
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}
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}
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// Assign a vreg to each return value.
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let mut retval_regs = vec![];
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for ret in &f.signature.returns {
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let v = next_vreg;
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next_vreg += 1;
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let regclass = I::rc_for_type(ret.value_type);
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let vreg = Reg::new_virtual(regclass, v);
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retval_regs.push(vreg);
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vcode.set_vreg_type(vreg.as_virtual_reg().unwrap(), ret.value_type);
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}
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Lower {
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f,
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vcode,
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num_uses,
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value_regs,
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retval_regs,
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next_vreg,
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}
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}
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fn gen_arg_setup(&mut self) {
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if let Some(entry_bb) = self.f.layout.entry_block() {
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debug!(
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"gen_arg_setup: entry BB {} args are:\n{:?}",
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entry_bb,
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self.f.dfg.block_params(entry_bb)
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);
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for (i, param) in self.f.dfg.block_params(entry_bb).iter().enumerate() {
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let reg = Writable::from_reg(self.value_regs[*param]);
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let insn = self.vcode.abi().gen_copy_arg_to_reg(i, reg);
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self.vcode.push(insn);
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}
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}
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}
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fn gen_retval_setup(&mut self, gen_ret_inst: GenerateReturn) {
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for (i, reg) in self.retval_regs.iter().enumerate() {
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let insn = self.vcode.abi().gen_copy_reg_to_retval(i, *reg);
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self.vcode.push(insn);
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}
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let inst = match gen_ret_inst {
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GenerateReturn::Yes => self.vcode.abi().gen_ret(),
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GenerateReturn::No => self.vcode.abi().gen_epilogue_placeholder(),
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};
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self.vcode.push(inst);
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}
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fn find_reachable_bbs(&self) -> SmallVec<[Block; 16]> {
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if let Some(entry) = self.f.layout.entry_block() {
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let mut ret = SmallVec::new();
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let mut queue = VecDeque::new();
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let mut visited = SecondaryMap::with_default(false);
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queue.push_back(entry);
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visited[entry] = true;
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while !queue.is_empty() {
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let b = queue.pop_front().unwrap();
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ret.push(b);
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let mut succs: SmallVec<[Block; 16]> = SmallVec::new();
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for inst in self.f.layout.block_insts(b) {
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if self.f.dfg[inst].opcode().is_branch() {
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succs.extend(branch_targets(self.f, b, inst).into_iter());
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}
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}
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for succ in succs.into_iter() {
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if !visited[succ] {
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queue.push_back(succ);
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visited[succ] = true;
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}
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}
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}
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ret
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} else {
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SmallVec::new()
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}
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}
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/// Lower the function.
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pub fn lower<B: LowerBackend<MInst = I>>(mut self, backend: &B) -> VCode<I> {
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// Find all reachable blocks.
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let mut bbs = self.find_reachable_bbs();
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// Work backward (reverse block order, reverse through each block), skipping insns with zero
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// uses.
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bbs.reverse();
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// This records a Block-to-BlockIndex map so that branch targets can be resolved.
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let mut next_bindex = self.vcode.init_bb_map(&bbs[..]);
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// Allocate a separate BlockIndex for each control-flow instruction so that we can create
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// the edge blocks later. Each entry for a control-flow inst is the edge block; the list
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// has (cf-inst, edge block, orig block) tuples.
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let mut edge_blocks_by_inst: SecondaryMap<Inst, Vec<BlockIndex>> =
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SecondaryMap::with_default(vec![]);
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let mut edge_blocks: Vec<(Inst, BlockIndex, Block)> = vec![];
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debug!("about to lower function: {:?}", self.f);
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debug!("bb map: {:?}", self.vcode.blocks_by_bb());
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for bb in bbs.iter() {
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for inst in self.f.layout.block_insts(*bb) {
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let op = self.f.dfg[inst].opcode();
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if op.is_branch() {
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// Find the original target.
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let mut add_succ = |next_bb| {
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let edge_block = next_bindex;
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next_bindex += 1;
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edge_blocks_by_inst[inst].push(edge_block);
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edge_blocks.push((inst, edge_block, next_bb));
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};
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for succ in branch_targets(self.f, *bb, inst).into_iter() {
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add_succ(succ);
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}
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}
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}
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}
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for bb in bbs.iter() {
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debug!("lowering bb: {}", bb);
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// If this is a return block, produce the return value setup.
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let last_insn = self.f.layout.block_insts(*bb).last().unwrap();
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let last_insn_opcode = self.f.dfg[last_insn].opcode();
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if last_insn_opcode.is_return() {
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let gen_ret = if last_insn_opcode == Opcode::Return {
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GenerateReturn::Yes
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} else {
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debug_assert!(last_insn_opcode == Opcode::FallthroughReturn);
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GenerateReturn::No
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};
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self.gen_retval_setup(gen_ret);
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self.vcode.end_ir_inst();
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}
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// Find the branches at the end first, and process those, if any.
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let mut branches: SmallVec<[Inst; 2]> = SmallVec::new();
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let mut targets: SmallVec<[BlockIndex; 2]> = SmallVec::new();
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for inst in self.f.layout.block_insts(*bb).rev() {
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debug!("lower: inst {}", inst);
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if edge_blocks_by_inst[inst].len() > 0 {
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branches.push(inst);
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for target in edge_blocks_by_inst[inst].iter().rev().cloned() {
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targets.push(target);
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}
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} else {
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// We've reached the end of the branches -- process all as a group, first.
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if branches.len() > 0 {
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let fallthrough = self.f.layout.next_block(*bb);
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let fallthrough = fallthrough.map(|bb| self.vcode.bb_to_bindex(bb));
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branches.reverse();
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targets.reverse();
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debug!(
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"lower_branch_group: targets = {:?} branches = {:?}",
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targets, branches
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);
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backend.lower_branch_group(
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&mut self,
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&branches[..],
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&targets[..],
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fallthrough,
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);
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self.vcode.end_ir_inst();
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branches.clear();
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targets.clear();
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}
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// Only codegen an instruction if it either has a side
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// effect, or has at least one use of one of its results.
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let num_uses = self.num_uses[inst];
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let side_effect = has_side_effect(self.f, inst);
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if side_effect || num_uses > 0 {
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backend.lower(&mut self, inst);
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self.vcode.end_ir_inst();
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} else {
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// If we're skipping the instruction, we need to dec-ref
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// its arguments.
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for arg in self.f.dfg.inst_args(inst) {
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let val = self.f.dfg.resolve_aliases(*arg);
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match self.f.dfg.value_def(val) {
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ValueDef::Result(src_inst, _) => {
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self.dec_use(src_inst);
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}
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_ => {}
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||||
}
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}
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}
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}
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}
|
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// There are possibly some branches left if the block contained only branches.
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if branches.len() > 0 {
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let fallthrough = self.f.layout.next_block(*bb);
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let fallthrough = fallthrough.map(|bb| self.vcode.bb_to_bindex(bb));
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branches.reverse();
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targets.reverse();
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debug!(
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"lower_branch_group: targets = {:?} branches = {:?}",
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targets, branches
|
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);
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backend.lower_branch_group(&mut self, &branches[..], &targets[..], fallthrough);
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self.vcode.end_ir_inst();
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branches.clear();
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targets.clear();
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}
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// If this is the entry block, produce the argument setup.
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if Some(*bb) == self.f.layout.entry_block() {
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self.gen_arg_setup();
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self.vcode.end_ir_inst();
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}
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let vcode_bb = self.vcode.end_bb();
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debug!("finished building bb: BlockIndex {}", vcode_bb);
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debug!("bb_to_bindex map says: {}", self.vcode.bb_to_bindex(*bb));
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assert!(vcode_bb == self.vcode.bb_to_bindex(*bb));
|
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if Some(*bb) == self.f.layout.entry_block() {
|
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self.vcode.set_entry(vcode_bb);
|
||||
}
|
||||
}
|
||||
|
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// Now create the edge blocks, with phi lowering (block parameter copies).
|
||||
for (inst, edge_block, orig_block) in edge_blocks.into_iter() {
|
||||
debug!(
|
||||
"creating edge block: inst {}, edge_block {}, orig_block {}",
|
||||
inst, edge_block, orig_block
|
||||
);
|
||||
|
||||
// Create a temporary for each block parameter.
|
||||
let phi_classes: Vec<(Type, RegClass)> = self
|
||||
.f
|
||||
.dfg
|
||||
.block_params(orig_block)
|
||||
.iter()
|
||||
.map(|p| self.f.dfg.value_type(*p))
|
||||
.map(|ty| (ty, I::rc_for_type(ty)))
|
||||
.collect();
|
||||
|
||||
// FIXME sewardj 2020Feb29: use SmallVec
|
||||
let mut src_regs = vec![];
|
||||
let mut dst_regs = vec![];
|
||||
|
||||
// Create all of the phi uses (reads) from jump args to temps.
|
||||
|
||||
// Round up all the source and destination regs
|
||||
for (i, arg) in self.f.dfg.inst_variable_args(inst).iter().enumerate() {
|
||||
let arg = self.f.dfg.resolve_aliases(*arg);
|
||||
debug!("jump arg {} is {}", i, arg);
|
||||
src_regs.push(self.value_regs[arg]);
|
||||
}
|
||||
for (i, param) in self.f.dfg.block_params(orig_block).iter().enumerate() {
|
||||
debug!("bb arg {} is {}", i, param);
|
||||
dst_regs.push(Writable::from_reg(self.value_regs[*param]));
|
||||
}
|
||||
debug_assert!(src_regs.len() == dst_regs.len());
|
||||
debug_assert!(phi_classes.len() == dst_regs.len());
|
||||
|
||||
// If, as is mostly the case, the source and destination register
|
||||
// sets are non overlapping, then we can copy directly, so as to
|
||||
// save the register allocator work.
|
||||
if !Set::<Reg>::from_vec(src_regs.clone()).intersects(&Set::<Reg>::from_vec(
|
||||
dst_regs.iter().map(|r| r.to_reg()).collect(),
|
||||
)) {
|
||||
for (dst_reg, (src_reg, (ty, _))) in
|
||||
dst_regs.iter().zip(src_regs.iter().zip(phi_classes))
|
||||
{
|
||||
self.vcode.push(I::gen_move(*dst_reg, *src_reg, ty));
|
||||
}
|
||||
} else {
|
||||
// There's some overlap, so play safe and copy via temps.
|
||||
|
||||
let tmp_regs: Vec<Writable<Reg>> = phi_classes
|
||||
.iter()
|
||||
.map(|&(ty, rc)| self.tmp(rc, ty)) // borrows `self` mutably.
|
||||
.collect();
|
||||
|
||||
debug!("phi_temps = {:?}", tmp_regs);
|
||||
debug_assert!(tmp_regs.len() == src_regs.len());
|
||||
|
||||
for (tmp_reg, (src_reg, &(ty, _))) in
|
||||
tmp_regs.iter().zip(src_regs.iter().zip(phi_classes.iter()))
|
||||
{
|
||||
self.vcode.push(I::gen_move(*tmp_reg, *src_reg, ty));
|
||||
}
|
||||
for (dst_reg, (tmp_reg, &(ty, _))) in
|
||||
dst_regs.iter().zip(tmp_regs.iter().zip(phi_classes.iter()))
|
||||
{
|
||||
self.vcode.push(I::gen_move(*dst_reg, tmp_reg.to_reg(), ty));
|
||||
}
|
||||
}
|
||||
|
||||
// Create the unconditional jump to the original target block.
|
||||
self.vcode
|
||||
.push(I::gen_jump(self.vcode.bb_to_bindex(orig_block)));
|
||||
|
||||
// End the IR inst and block. (We lower this as if it were one IR instruction so that
|
||||
// we can emit machine instructions in forward order.)
|
||||
self.vcode.end_ir_inst();
|
||||
let blocknum = self.vcode.end_bb();
|
||||
assert!(blocknum == edge_block);
|
||||
}
|
||||
|
||||
// Now that we've emitted all instructions into the VCodeBuilder, let's build the VCode.
|
||||
self.vcode.build()
|
||||
}
|
||||
|
||||
/// Reduce the use-count of an IR instruction. Use this when, e.g., isel incorporates the
|
||||
/// computation of an input instruction directly, so that input instruction has one
|
||||
/// fewer use.
|
||||
fn dec_use(&mut self, ir_inst: Inst) {
|
||||
assert!(self.num_uses[ir_inst] > 0);
|
||||
self.num_uses[ir_inst] -= 1;
|
||||
debug!(
|
||||
"incref: ir_inst {} now has {} uses",
|
||||
ir_inst, self.num_uses[ir_inst]
|
||||
);
|
||||
}
|
||||
|
||||
/// Increase the use-count of an IR instruction. Use this when, e.g., isel incorporates
|
||||
/// the computation of an input instruction directly, so that input instruction's
|
||||
/// inputs are now used directly by the merged instruction.
|
||||
fn inc_use(&mut self, ir_inst: Inst) {
|
||||
self.num_uses[ir_inst] += 1;
|
||||
debug!(
|
||||
"decref: ir_inst {} now has {} uses",
|
||||
ir_inst, self.num_uses[ir_inst]
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
impl<'a, I: VCodeInst> LowerCtx<I> for Lower<'a, I> {
|
||||
/// Get the instdata for a given IR instruction.
|
||||
fn data(&self, ir_inst: Inst) -> &InstructionData {
|
||||
&self.f.dfg[ir_inst]
|
||||
}
|
||||
|
||||
/// Get the controlling type for a polymorphic IR instruction.
|
||||
fn ty(&self, ir_inst: Inst) -> Type {
|
||||
self.f.dfg.ctrl_typevar(ir_inst)
|
||||
}
|
||||
|
||||
/// Emit a machine instruction.
|
||||
fn emit(&mut self, mach_inst: I) {
|
||||
self.vcode.push(mach_inst);
|
||||
}
|
||||
|
||||
/// Indicate that a merge has occurred.
|
||||
fn merged(&mut self, from_inst: Inst) {
|
||||
debug!("merged: inst {}", from_inst);
|
||||
// First, inc-ref all inputs of `from_inst`, because they are now used
|
||||
// directly by `into_inst`.
|
||||
for arg in self.f.dfg.inst_args(from_inst) {
|
||||
let arg = self.f.dfg.resolve_aliases(*arg);
|
||||
match self.f.dfg.value_def(arg) {
|
||||
ValueDef::Result(src_inst, _) => {
|
||||
debug!(" -> inc-reffing src inst {}", src_inst);
|
||||
self.inc_use(src_inst);
|
||||
}
|
||||
_ => {}
|
||||
}
|
||||
}
|
||||
// Then, dec-ref the merged instruction itself. It still retains references
|
||||
// to its arguments (inc-ref'd above). If its refcount has reached zero,
|
||||
// it will be skipped during emission and its args will be dec-ref'd at that
|
||||
// time.
|
||||
self.dec_use(from_inst);
|
||||
}
|
||||
|
||||
/// Get the producing instruction, if any, and output number, for the `idx`th input to the
|
||||
/// given IR instruction.
|
||||
fn input_inst(&self, ir_inst: Inst, idx: usize) -> Option<(Inst, usize)> {
|
||||
let val = self.f.dfg.inst_args(ir_inst)[idx];
|
||||
let val = self.f.dfg.resolve_aliases(val);
|
||||
match self.f.dfg.value_def(val) {
|
||||
ValueDef::Result(src_inst, result_idx) => Some((src_inst, result_idx)),
|
||||
_ => None,
|
||||
}
|
||||
}
|
||||
|
||||
/// Map a Value to its associated writable (probably virtual) Reg.
|
||||
fn value_to_writable_reg(&self, val: Value) -> Writable<Reg> {
|
||||
let val = self.f.dfg.resolve_aliases(val);
|
||||
Writable::from_reg(self.value_regs[val])
|
||||
}
|
||||
|
||||
/// Map a Value to its associated (probably virtual) Reg.
|
||||
fn value_to_reg(&self, val: Value) -> Reg {
|
||||
let val = self.f.dfg.resolve_aliases(val);
|
||||
self.value_regs[val]
|
||||
}
|
||||
|
||||
/// Get the `idx`th input to the given IR instruction as a virtual register.
|
||||
fn input(&self, ir_inst: Inst, idx: usize) -> Reg {
|
||||
let val = self.f.dfg.inst_args(ir_inst)[idx];
|
||||
let val = self.f.dfg.resolve_aliases(val);
|
||||
self.value_to_reg(val)
|
||||
}
|
||||
|
||||
/// Get the `idx`th output of the given IR instruction as a virtual register.
|
||||
fn output(&self, ir_inst: Inst, idx: usize) -> Writable<Reg> {
|
||||
let val = self.f.dfg.inst_results(ir_inst)[idx];
|
||||
self.value_to_writable_reg(val)
|
||||
}
|
||||
|
||||
/// Get a new temp.
|
||||
fn tmp(&mut self, rc: RegClass, ty: Type) -> Writable<Reg> {
|
||||
let v = self.next_vreg;
|
||||
self.next_vreg += 1;
|
||||
let vreg = Reg::new_virtual(rc, v);
|
||||
self.vcode.set_vreg_type(vreg.as_virtual_reg().unwrap(), ty);
|
||||
Writable::from_reg(vreg)
|
||||
}
|
||||
|
||||
/// Get the number of inputs for the given IR instruction.
|
||||
fn num_inputs(&self, ir_inst: Inst) -> usize {
|
||||
self.f.dfg.inst_args(ir_inst).len()
|
||||
}
|
||||
|
||||
/// Get the number of outputs for the given IR instruction.
|
||||
fn num_outputs(&self, ir_inst: Inst) -> usize {
|
||||
self.f.dfg.inst_results(ir_inst).len()
|
||||
}
|
||||
|
||||
/// Get the type for an instruction's input.
|
||||
fn input_ty(&self, ir_inst: Inst, idx: usize) -> Type {
|
||||
let val = self.f.dfg.inst_args(ir_inst)[idx];
|
||||
let val = self.f.dfg.resolve_aliases(val);
|
||||
self.f.dfg.value_type(val)
|
||||
}
|
||||
|
||||
/// Get the type for an instruction's output.
|
||||
fn output_ty(&self, ir_inst: Inst, idx: usize) -> Type {
|
||||
self.f.dfg.value_type(self.f.dfg.inst_results(ir_inst)[idx])
|
||||
}
|
||||
|
||||
/// Get the number of block params.
|
||||
fn num_bb_params(&self, bb: Block) -> usize {
|
||||
self.f.dfg.block_params(bb).len()
|
||||
}
|
||||
|
||||
/// Get the register for a block param.
|
||||
fn bb_param(&self, bb: Block, idx: usize) -> Reg {
|
||||
let val = self.f.dfg.block_params(bb)[idx];
|
||||
self.value_regs[val]
|
||||
}
|
||||
|
||||
/// Get the register for a return value.
|
||||
fn retval(&self, idx: usize) -> Writable<Reg> {
|
||||
Writable::from_reg(self.retval_regs[idx])
|
||||
}
|
||||
|
||||
/// Get the target for a call instruction, as an `ExternalName`.
|
||||
fn call_target<'b>(&'b self, ir_inst: Inst) -> Option<&'b ExternalName> {
|
||||
match &self.f.dfg[ir_inst] {
|
||||
&InstructionData::Call { func_ref, .. }
|
||||
| &InstructionData::FuncAddr { func_ref, .. } => {
|
||||
let funcdata = &self.f.dfg.ext_funcs[func_ref];
|
||||
Some(&funcdata.name)
|
||||
}
|
||||
_ => None,
|
||||
}
|
||||
}
|
||||
/// Get the signature for a call or call-indirect instruction.
|
||||
fn call_sig<'b>(&'b self, ir_inst: Inst) -> Option<&'b Signature> {
|
||||
match &self.f.dfg[ir_inst] {
|
||||
&InstructionData::Call { func_ref, .. } => {
|
||||
let funcdata = &self.f.dfg.ext_funcs[func_ref];
|
||||
Some(&self.f.dfg.signatures[funcdata.signature])
|
||||
}
|
||||
&InstructionData::CallIndirect { sig_ref, .. } => Some(&self.f.dfg.signatures[sig_ref]),
|
||||
_ => None,
|
||||
}
|
||||
}
|
||||
|
||||
/// Get the symbol name and offset for a symbol_value instruction.
|
||||
fn symbol_value<'b>(&'b self, ir_inst: Inst) -> Option<(&'b ExternalName, i64)> {
|
||||
match &self.f.dfg[ir_inst] {
|
||||
&InstructionData::UnaryGlobalValue { global_value, .. } => {
|
||||
let gvdata = &self.f.global_values[global_value];
|
||||
match gvdata {
|
||||
&GlobalValueData::Symbol {
|
||||
ref name,
|
||||
ref offset,
|
||||
..
|
||||
} => {
|
||||
let offset = offset.bits();
|
||||
Some((name, offset))
|
||||
}
|
||||
_ => None,
|
||||
}
|
||||
}
|
||||
_ => None,
|
||||
}
|
||||
}
|
||||
|
||||
/// Returns the memory flags of a given memory access.
|
||||
fn memflags(&self, ir_inst: Inst) -> Option<MemFlags> {
|
||||
match &self.f.dfg[ir_inst] {
|
||||
&InstructionData::Load { flags, .. }
|
||||
| &InstructionData::LoadComplex { flags, .. }
|
||||
| &InstructionData::Store { flags, .. }
|
||||
| &InstructionData::StoreComplex { flags, .. } => Some(flags),
|
||||
_ => None,
|
||||
}
|
||||
}
|
||||
|
||||
/// Get the source location for a given instruction.
|
||||
fn srcloc(&self, ir_inst: Inst) -> SourceLoc {
|
||||
self.f.srclocs[ir_inst]
|
||||
}
|
||||
}
|
||||
|
||||
fn branch_targets(f: &Function, block: Block, inst: Inst) -> SmallVec<[Block; 16]> {
|
||||
let mut ret = SmallVec::new();
|
||||
if f.dfg[inst].opcode() == Opcode::Fallthrough {
|
||||
ret.push(f.layout.next_block(block).unwrap());
|
||||
} else {
|
||||
match &f.dfg[inst] {
|
||||
&InstructionData::Jump { destination, .. }
|
||||
| &InstructionData::Branch { destination, .. }
|
||||
| &InstructionData::BranchInt { destination, .. }
|
||||
| &InstructionData::BranchIcmp { destination, .. }
|
||||
| &InstructionData::BranchFloat { destination, .. } => {
|
||||
ret.push(destination);
|
||||
}
|
||||
&InstructionData::BranchTable {
|
||||
destination, table, ..
|
||||
} => {
|
||||
ret.push(destination);
|
||||
for dest in f.jump_tables[table].as_slice() {
|
||||
ret.push(*dest);
|
||||
}
|
||||
}
|
||||
_ => {}
|
||||
}
|
||||
}
|
||||
ret
|
||||
}
|
||||
Reference in New Issue
Block a user