ARM64 backend, part 3 / 11: MachInst infrastructure.
This patch adds the MachInst, or Machine Instruction, infrastructure. This is the machine-independent portion of the new backend design. It contains the implementation of the "vcode" (virtual-registerized code) container, the top-level lowering algorithm and compilation pipeline, and the trait definitions that the machine backends will fill in. This backend infrastructure is included in the compilation of the `codegen` crate, but it is not yet tied into the public APIs; that patch will come last, after all the other pieces are filled in. This patch contains code written by Julian Seward <jseward@acm.org> and Benjamin Bouvier <public@benj.me>, originally developed on a side-branch before rebasing and condensing into this patch series. See the `arm64` branch at `https://github.com/cfallin/wasmtime` for original development history. Co-authored-by: Julian Seward <jseward@acm.org> Co-authored-by: Benjamin Bouvier <public@benj.me>
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@@ -55,9 +55,10 @@ pub use crate::isa::stack::{StackBase, StackBaseMask, StackRef};
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use crate::binemit;
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use crate::flowgraph;
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use crate::ir;
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use crate::isa::enc_tables::Encodings;
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pub use crate::isa::enc_tables::Encodings;
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#[cfg(feature = "unwind")]
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use crate::isa::fde::RegisterMappingError;
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use crate::machinst::MachBackend;
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use crate::regalloc;
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use crate::result::CodegenResult;
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use crate::settings;
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@@ -400,6 +401,11 @@ pub trait TargetIsa: fmt::Display + Send + Sync {
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) {
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// No-op by default
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}
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/// Get the new-style MachBackend, if this is an adapter around one.
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fn get_mach_backend(&self) -> Option<&dyn MachBackend> {
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None
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}
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}
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impl Debug for &dyn TargetIsa {
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