Implement binary emission of RISC-V return instructions.

The return address is now always supplied in %x1, so the return address
predictor will recognize the jalr as a return and not some indirect
branch.

lib/cretonne/meta/isa/riscv/recipes.py

@@ -110,7 +110,7 @@ Iicmp = EncRecipe(
 # I-type encoding for `jalr` as a return instruction. We won't use the
 # immediate offset.
 # The variable return values are not encoded.
-Iret = EncRecipe('Iret', MultiAry, size=4, ins=GPR, outs=())
+Iret = EncRecipe('Iret', MultiAry, size=4, ins=(), outs=())
 
 # U-type instructions have a 20-bit immediate that targets bits 12-31.
 U = EncRecipe(

lib/cretonne/src/isa/riscv/binemit.rs

@@ -172,8 +172,14 @@ fn recipe_iicmp<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut C
     }
 }
 
-fn recipe_iret<CS: CodeSink + ?Sized>(_func: &Function, _inst: Inst, _sink: &mut CS) {
-    unimplemented!()
+fn recipe_iret<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
+    // Return instructions are always a jalr to %x1.
+    // The return address is provided as a special-purpose link argument.
+    put_i(func.encodings[inst].bits(),
+          1, // rs1 = %x1
+          0, // no offset.
+          0, // rd = %x0: no address written.
+          sink);
 }
 
 /// U-type instructions.