Implement binary emission of RISC-V return instructions.

The return address is now always supplied in %x1, so the return address
predictor will recognize the jalr as a return and not some indirect
branch.

cranelift/filetests/isa/riscv/binary32.cton

@@ -2,10 +2,10 @@
 test binemit
 isa riscv
 
-function RV32I() {
+function RV32I(i32 link [%x1]) -> i32 link [%x1] {
     fn0 = function foo()
 
-ebb0:
+ebb0(v9999: i32):
     [-,%x10]            v1 = iconst.i32 1
     [-,%x21]            v2 = iconst.i32 2
 
@@ -83,7 +83,10 @@ ebb0:
     call fn0()                                  ; bin: Call(fn0) 000000ef
 
     brz v1, ebb3
-    fallthrough ebb1
+    brnz v1, ebb1
+
+    ; jalr %x0, %x1, 0
+    return v9999                        ; bin: 00008067
 
 ebb1:
     ; beq 0x000