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Add SIB/offset for ABCD stores too;

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This commit is contained in:
Benjamin Bouvier
2018-11-14 11:49:34 +01:00
committed by Dan Gohman
parent b170b74b65
commit d45e8b5830
1 changed files with 24 additions and 3 deletions
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27
lib/codegen/meta-python/isa/x86/recipes.py
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@@ -854,12 +854,21 @@ st_abcd = TailRecipe(
instp=IsEqual(Store.offset, 0), instp=IsEqual(Store.offset, 0),
when_prefixed=st, when_prefixed=st,
clobbers_flags=False, clobbers_flags=False,
compute_size="size_plus_maybe_sib_or_offset_for_in_reg_1",
emit=''' emit='''
if !flags.notrap() { if !flags.notrap() {
sink.trap(TrapCode::HeapOutOfBounds, func.srclocs[inst]); sink.trap(TrapCode::HeapOutOfBounds, func.srclocs[inst]);
} }
PUT_OP(bits, rex2(in_reg1, in_reg0), sink); PUT_OP(bits, rex2(in_reg1, in_reg0), sink);
modrm_rm(in_reg1, in_reg0, sink); if needs_sib_byte(in_reg1) {
modrm_sib(in_reg0, sink);
sib_noindex(in_reg1, sink);
} else if needs_offset(in_reg1) {
modrm_disp8(in_reg1, in_reg0, sink);
sink.put1(0);
} else {
modrm_rm(in_reg1, in_reg0, sink);
}
''') ''')
# XX /r register-indirect store with index and no offset. # XX /r register-indirect store with index and no offset.
@@ -977,12 +986,18 @@ stDisp8_abcd = TailRecipe(
instp=IsSignedInt(Store.offset, 8), instp=IsSignedInt(Store.offset, 8),
when_prefixed=stDisp8, when_prefixed=stDisp8,
clobbers_flags=False, clobbers_flags=False,
compute_size="size_plus_maybe_sib_for_in_reg_1",
emit=''' emit='''
if !flags.notrap() { if !flags.notrap() {
sink.trap(TrapCode::HeapOutOfBounds, func.srclocs[inst]); sink.trap(TrapCode::HeapOutOfBounds, func.srclocs[inst]);
} }
PUT_OP(bits, rex2(in_reg1, in_reg0), sink); PUT_OP(bits, rex2(in_reg1, in_reg0), sink);
modrm_disp8(in_reg1, in_reg0, sink); if needs_sib_byte(in_reg1) {
modrm_sib_disp8(in_reg0, sink);
sib_noindex(in_reg1, sink);
} else {
modrm_disp8(in_reg1, in_reg0, sink);
}
let offset: i32 = offset.into(); let offset: i32 = offset.into();
sink.put1(offset as u8); sink.put1(offset as u8);
''') ''')
@@ -1089,12 +1104,18 @@ stDisp32_abcd = TailRecipe(
'stDisp32_abcd', Store, base_size=5, ins=(ABCD, GPR), outs=(), 'stDisp32_abcd', Store, base_size=5, ins=(ABCD, GPR), outs=(),
when_prefixed=stDisp32, when_prefixed=stDisp32,
clobbers_flags=False, clobbers_flags=False,
compute_size="size_plus_maybe_sib_for_in_reg_1",
emit=''' emit='''
if !flags.notrap() { if !flags.notrap() {
sink.trap(TrapCode::HeapOutOfBounds, func.srclocs[inst]); sink.trap(TrapCode::HeapOutOfBounds, func.srclocs[inst]);
} }
PUT_OP(bits, rex2(in_reg1, in_reg0), sink); PUT_OP(bits, rex2(in_reg1, in_reg0), sink);
modrm_disp32(in_reg1, in_reg0, sink); if needs_sib_byte(in_reg1) {
modrm_sib_disp32(in_reg0, sink);
sib_noindex(in_reg1, sink);
} else {
modrm_disp32(in_reg1, in_reg0, sink);
}
let offset: i32 = offset.into(); let offset: i32 = offset.into();
sink.put4(offset as u32); sink.put4(offset as u32);
''') ''')