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intel isa: comments to explain rip-relative addressing encoding

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This commit is contained in:
Pat Hickey
2017-12-12 15:13:11 -08:00
committed by Jakob Stoklund Olesen
parent ed81bc21be
commit d444044e9e
2 changed files with 10 additions and 3 deletions
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6
lib/cretonne/meta/isa/intel/recipes.py
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@@ -560,11 +560,11 @@ allones_fnaddr8 = TailRecipe(
got_fnaddr8 = TailRecipe( got_fnaddr8 = TailRecipe(
'got_fnaddr8', FuncAddr, size=5, ins=(), outs=GPR, 'got_fnaddr8', FuncAddr, size=5, ins=(), outs=GPR,
# rex2 is a hack at the moment to get one that sets the `r` bit in rex # rex2 gets passed 0 for r/m register because the upper bit of
# rm for modrm_rm is 5 to get RIP-relative addressing # r/m doesnt get decoded when in rip-relative addressing mode.
emit=''' emit='''
PUT_OP(bits, rex2(0, out_reg0), sink); PUT_OP(bits, rex2(0, out_reg0), sink);
modrm_rm(5, out_reg0, sink); modrm_riprel(out_reg0, sink);
sink.reloc_external(Reloc::IntelGotPCRel4, sink.reloc_external(Reloc::IntelGotPCRel4,
&func.dfg.ext_funcs[func_ref].name); &func.dfg.ext_funcs[func_ref].name);
sink.put4(0); sink.put4(0);

7
lib/cretonne/src/isa/intel/binemit.rs
View File

@@ -180,6 +180,13 @@ fn modrm_rm<CS: CodeSink + ?Sized>(rm: RegUnit, reg: RegUnit, sink: &mut CS) {
sink.put1(b); sink.put1(b);
} }
/// Emit a mode 00 Mod/RM byte, with a rip-relative displacement in 64-bit mode. Effective address
/// is calculated by adding displacement to 64-bit rip of next instruction. See intel Sw dev manual
/// section 2.2.1.6.
fn modrm_riprel<CS: CodeSink + ?Sized>(reg: RegUnit, sink: &mut CS) {
modrm_rm(0b101, reg, sink)
}
/// Emit a mode 01 ModR/M byte. This is a register-indirect addressing mode with 8-bit /// Emit a mode 01 ModR/M byte. This is a register-indirect addressing mode with 8-bit
/// displacement. /// displacement.
/// Register %rsp is invalid for `rm`. It indicates the presence of a SIB byte. /// Register %rsp is invalid for `rm`. It indicates the presence of a SIB byte.