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x64: Mask shift amounts for small types (#4752)

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* x64: Mask shift amounts for small types

* cranelift: Disable i128 shifts in fuzzer again

They are fixed. But we had a bunch of fuzzgen issues come in, and we don't want to accidentaly mark them as fixed

* cranelift: Avoid masking shifts for 32 and 64 bit cases

* cranelift: Add const shift tests and fix them

* cranelift: Remove const `rotl` cases

Now that `put_masked_in_imm8_gpr` works properly we can simplify rotl/rotr
This commit is contained in:
Afonso Bordado
2022-08-24 18:31:38 +01:00
committed by GitHub
parent 9cb987c678
commit d394edcefe
10 changed files with 1920 additions and 117 deletions
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7
cranelift/codegen/src/isa/x64/inst.isle
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@@ -1057,7 +1057,12 @@
;;
;; This is used when lowering various shifts and rotates.
(decl put_masked_in_imm8_gpr (Value Type) Imm8Gpr)
(extern constructor put_masked_in_imm8_gpr put_masked_in_imm8_gpr)
(rule (put_masked_in_imm8_gpr (u64_from_iconst amt) ty)
(const_to_type_masked_imm8 amt ty))
(rule (put_masked_in_imm8_gpr amt (fits_in_16 ty))
(x64_and $I64 (value_regs_get_gpr amt 0) (RegMemImm.Imm (shift_mask ty))))
(rule (put_masked_in_imm8_gpr amt ty)
(value_regs_get_gpr amt 0))
;; Condition codes
(type CC extern