Add jump encodings to RISC-V.

Fix a bug in gen_encoding.py when dealing with non-polymorphic
instructions where the type variable is None in Python, VOID in Rust.

lib/cretonne/meta/isa/riscv/recipes.py

@@ -12,7 +12,7 @@ from __future__ import absolute_import
 from cdsl.isa import EncRecipe
 from cdsl.predicates import IsSignedInt
 from base.formats import Binary, BinaryImm, MultiAry, IntCompare, IntCompareImm
-from base.formats import UnaryImm, BranchIcmp, Branch
+from base.formats import UnaryImm, BranchIcmp, Branch, Jump
 from .registers import GPR
 
 # The low 7 bits of a RISC-V instruction is the base opcode. All 32-bit
@@ -47,6 +47,11 @@ def JALR(funct3=0):
     return 0b11001 | (funct3 << 5)
 
 
+def JAL():
+    # type: () -> int
+    return 0b11011
+
+
 def OPIMM(funct3, funct7=0):
     # type: (int, int) -> int
     assert funct3 <= 0b111
@@ -112,6 +117,9 @@ U = EncRecipe(
         'U', UnaryImm, size=4, ins=(), outs=GPR,
         instp=IsSignedInt(UnaryImm.imm, 32, 12))
 
+# UJ-type unconditional branch instructions.
+UJ = EncRecipe('UJ', Jump, size=4, ins=(), outs=(), branch_range=(0, 21))
+
 # SB-type branch instructions.
 # TODO: These instructions have a +/- 4 KB branch range. How to encode that
 # constraint?