Add the br_icmp instruction.

This instruction behaves like icmp fused with brnz, and it can be used
to represent fused compare+branch instruction on Intel when optimizing
for macro-op fusion.

RISC-V provides compare-and-branch instructions directly, and it is
needed there too.

filetests/parser/tiny.cton

@@ -56,6 +56,7 @@ ebb0(vx0: i32, vx1: i32):
     v1 = icmp ult, vx0, vx1
     v2 = icmp_imm sge, vx0, -12
     v3 = irsub_imm vx1, 45
+    br_icmp eq, vx0, vx1, ebb0(vx1, vx0)
 }
 ; sameln: function icmp(i32, i32) {
 ; nextln: ebb0(vx0: i32, vx1: i32):
@@ -63,6 +64,7 @@ ebb0(vx0: i32, vx1: i32):
 ; nextln:     v1 = icmp ult, vx0, vx1
 ; nextln:     v2 = icmp_imm sge, vx0, -12
 ; nextln:     v3 = irsub_imm vx1, 45
+; nextln:     br_icmp eq, vx0, vx1, ebb0(vx1, vx0)
 ; nextln: }
 
 ; Floating condition codes.