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Cranelift AArch64: Further integral constant fixes (#4530)

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Copyright (c) 2022, Arm Limited.
This commit is contained in:
Anton Kirilov
2022-07-26 17:35:06 +01:00
committed by GitHub
parent 1935428af7
commit d041c4b376
4 changed files with 188 additions and 32 deletions
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8
cranelift/filetests/filetests/isa/aarch64/bitops.clif
View File

@@ -111,7 +111,7 @@ block0(v0: i128):
; clz x8, x0
; lsr x10, x6, #6
; madd x0, x8, x10, x6
; movz x1, #0
; movz w1, #0
; ret
function %c(i8) -> i8 {
@@ -173,7 +173,7 @@ block0(v0: i128):
; subs xzr, x8, #63
; csel x1, x14, xzr, eq
; add x0, x1, x8
; movz x1, #0
; movz w1, #0
; ret
function %d(i8) -> i8 {
@@ -235,7 +235,7 @@ block0(v0: i128):
; clz x12, x8
; lsr x14, x10, #6
; madd x0, x12, x14, x10
; movz x1, #0
; movz w1, #0
; ret
function %d(i128) -> i128 {
@@ -253,7 +253,7 @@ block0(v0: i128):
; cnt v11.16b, v6.16b
; addv b13, v11.16b
; umov w0, v13.b[0]
; movz x1, #0
; movz w1, #0
; ldp d11, d13, [sp], #16
; ldp fp, lr, [sp], #16
; ret

16
cranelift/filetests/filetests/isa/aarch64/extend-op.clif
View File

@@ -33,7 +33,7 @@ block0(v0: i64):
}
; block0:
; movz x1, #0
; movz w1, #0
; ret
function %i128_sextend_i64(i64) -> i128 {
@@ -54,7 +54,7 @@ block0(v0: i32):
; block0:
; mov w0, w0
; movz x1, #0
; movz w1, #0
; ret
function %i128_sextend_i32(i32) -> i128 {
@@ -76,7 +76,7 @@ block0(v0: i16):
; block0:
; uxth w0, w0
; movz x1, #0
; movz w1, #0
; ret
function %i128_sextend_i16(i16) -> i128 {
@@ -98,7 +98,7 @@ block0(v0: i8):
; block0:
; uxtb w0, w0
; movz x1, #0
; movz w1, #0
; ret
function %i128_sextend_i8(i8) -> i128 {
@@ -154,7 +154,7 @@ block0(v0: i8x16):
; block0:
; umov w0, v0.b[1]
; movz x1, #0
; movz w1, #0
; ret
function %i8x16_sextend_i16(i8x16) -> i16 {
@@ -233,7 +233,7 @@ block0(v0: i16x8):
; block0:
; umov w0, v0.h[1]
; movz x1, #0
; movz w1, #0
; ret
function %i16x8_sextend_i32(i16x8) -> i32 {
@@ -290,7 +290,7 @@ block0(v0: i32x4):
; block0:
; mov w0, v0.s[1]
; movz x1, #0
; movz w1, #0
; ret
function %i32x4_sextend_i64(i32x4) -> i64 {
@@ -325,7 +325,7 @@ block0(v0: i64x2):
; block0:
; mov x0, v0.d[1]
; movz x1, #0
; movz w1, #0
; ret
function %i64x2_sextend_i128(i64x2) -> i128 {