We now parse and record a ValueLoc for each SSA value result of each instruction. Code currently not passing tests.
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committed by
Jakob Stoklund Olesen
parent
bc1901b766
commit
cfdecfdcbf
@@ -15,11 +15,10 @@ ebb1(v0: i32, v1: i32):
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}
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; sameln: function foo(i32, i32) {
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; nextln: $ebb1($v0: i32, $v1: i32):
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; nextln: [-]$WS $v2 = iadd $v0, $v1
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; nextln: [-,-]$WS $v2 = iadd $v0, $v1
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; nextln: [-]$WS trap
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; nextln: [R#1234]$WS $v6, $v7 = iadd_cout $v2, $v0
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; TODO Add the full encoding information available: instruction recipe name and architectural registers if specified
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; nextln: [Rshamt#beef]$WS $v8 = ishl_imm $v6, 2
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; nextln: [-]$WS $v9 = iadd $v8, $v7
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; nextln: [R#1234,%x5,%x11]$WS $v6, $v7 = iadd_cout $v2, $v0
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; nextln: [Rshamt#beef,%x25]$WS $v8 = ishl_imm $v6, 2
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; nextln: [-,-]$WS $v9 = iadd $v8, $v7
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; nextln: [Iret#05]$WS return $v0, $v8
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; nextln: }
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