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Add a DynRex recipe type for x86, decreasing the number of recipes (#1298)

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This patch adds a third mode for templates: REX inference is requestable
at template instantiation time. This reduces the number of recipes
by removing rex()/nonrex() redundancy for many instructions.
This commit is contained in:
Sean Stangl
2019-12-19 15:49:34 -07:00
committed by GitHub
parent b486289ab8
commit cf9e762f16
13 changed files with 875 additions and 514 deletions
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38
cranelift/filetests/filetests/regalloc/coloring-227.clif
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@@ -8,7 +8,7 @@ function %pr227(i32 [%rdi], i32 [%rsi], i32 [%rdx], i32 [%rcx], i64 vmctx [%r8])
ebb0(v0: i32, v1: i32, v2: i32, v3: i32, v4: i64):
[RexOp1pu_id#b8] v5 = iconst.i32 0
[RexOp1pu_id#b8] v6 = iconst.i32 0
[RexOp1tjccb#74] brz v6, ebb10
[DynRexOp1tjccb#74] brz v6, ebb10
[Op1jmpb#eb] jump ebb3(v5, v5, v5, v5, v5, v5, v0, v1, v2, v3)
ebb3(v15: i32, v17: i32, v25: i32, v31: i32, v40: i32, v47: i32, v54: i32, v61: i32, v68: i32, v75: i32):
@@ -16,33 +16,33 @@ function %pr227(i32 [%rdi], i32 [%rsi], i32 [%rdx], i32 [%rcx], i64 vmctx [%r8])
ebb6:
[RexOp1pu_id#b8] v8 = iconst.i32 0
[RexOp1tjccb#75] brnz v8, ebb5
[DynRexOp1tjccb#75] brnz v8, ebb5
[Op1jmpb#eb] jump ebb20
ebb20:
[RexOp1pu_id#b8] v9 = iconst.i32 0
[RexOp1pu_id#b8] v11 = iconst.i32 0
[RexOp1icscc#39] v12 = icmp.i32 eq v15, v11
[DynRexOp1icscc#39] v12 = icmp.i32 eq v15, v11
[RexOp2urm_noflags#4b6] v13 = bint.i32 v12
[RexOp1rr#21] v14 = band v9, v13
[RexOp1tjccb#75] brnz v14, ebb6
[DynRexOp1rr#21] v14 = band v9, v13
[DynRexOp1tjccb#75] brnz v14, ebb6
[Op1jmpb#eb] jump ebb7
ebb7:
[RexOp1tjccb#74] brz.i32 v17, ebb8
[DynRexOp1tjccb#74] brz.i32 v17, ebb8
[Op1jmpb#eb] jump ebb17
ebb17:
[RexOp1pu_id#b8] v18 = iconst.i32 0
[RexOp1tjccb#74] brz v18, ebb9
[DynRexOp1tjccb#74] brz v18, ebb9
[Op1jmpb#eb] jump ebb16
ebb16:
[RexOp1pu_id#b8] v21 = iconst.i32 0
[RexOp1umr#89] v79 = uextend.i64 v5
[RexOp1r_ib#8083] v80 = iadd_imm.i64 v4, 0
[DynRexOp1r_ib#8083] v80 = iadd_imm.i64 v4, 0
[RexOp1ld#808b] v81 = load.i64 v80
[RexOp1rr#8001] v22 = iadd v81, v79
[DynRexOp1rr#8001] v22 = iadd v81, v79
[RexMp1st#189] istore16 v21, v22
[Op1jmpb#eb] jump ebb9
@@ -52,8 +52,8 @@ function %pr227(i32 [%rdi], i32 [%rsi], i32 [%rdx], i32 [%rcx], i64 vmctx [%r8])
ebb8:
[RexOp1pu_id#b8] v27 = iconst.i32 3
[RexOp1pu_id#b8] v28 = iconst.i32 4
[RexOp1rr#09] v35 = bor.i32 v31, v13
[RexOp1tjccb#75] brnz v35, ebb15(v27)
[DynRexOp1rr#09] v35 = bor.i32 v31, v13
[DynRexOp1tjccb#75] brnz v35, ebb15(v27)
[Op1jmpb#eb] jump ebb15(v28)
ebb15(v36: i32):
@@ -71,24 +71,24 @@ function %pr227(i32 [%rdi], i32 [%rsi], i32 [%rdx], i32 [%rcx], i64 vmctx [%r8])
ebb2(v7: i32, v45: i32, v52: i32, v59: i32, v66: i32, v73: i32):
[RexOp1pu_id#b8] v44 = iconst.i32 0
[RexOp1tjccb#74] brz v44, ebb12
[DynRexOp1tjccb#74] brz v44, ebb12
[Op1jmpb#eb] jump ebb18
ebb18:
[RexOp1pu_id#b8] v50 = iconst.i32 11
[RexOp1tjccb#74] brz v50, ebb14
[DynRexOp1tjccb#74] brz v50, ebb14
[Op1jmpb#eb] jump ebb19
ebb19:
[RexOp1umr#89] v82 = uextend.i64 v52
[RexOp1r_ib#8083] v83 = iadd_imm.i64 v4, 0
[DynRexOp1r_ib#8083] v83 = iadd_imm.i64 v4, 0
[RexOp1ld#808b] v84 = load.i64 v83
[RexOp1rr#8001] v57 = iadd v84, v82
[DynRexOp1rr#8001] v57 = iadd v84, v82
[RexOp1ld#8b] v58 = load.i32 v57
[RexOp1umr#89] v85 = uextend.i64 v58
[RexOp1r_ib#8083] v86 = iadd_imm.i64 v4, 0
[DynRexOp1r_ib#8083] v86 = iadd_imm.i64 v4, 0
[RexOp1ld#808b] v87 = load.i64 v86
[RexOp1rr#8001] v64 = iadd v87, v85
[DynRexOp1rr#8001] v64 = iadd v87, v85
[RexOp1st#88] istore8 v59, v64
[RexOp1pu_id#b8] v65 = iconst.i32 0
[Op1jmpb#eb] jump ebb13(v65)
@@ -98,9 +98,9 @@ function %pr227(i32 [%rdi], i32 [%rsi], i32 [%rdx], i32 [%rcx], i64 vmctx [%r8])
ebb13(v51: i32):
[RexOp1umr#89] v88 = uextend.i64 v45
[RexOp1r_ib#8083] v89 = iadd_imm.i64 v4, 0
[DynRexOp1r_ib#8083] v89 = iadd_imm.i64 v4, 0
[RexOp1ld#808b] v90 = load.i64 v89
[RexOp1rr#8001] v71 = iadd v90, v88
[DynRexOp1rr#8001] v71 = iadd v90, v88
[RexOp1st#89] store v51, v71
[Op1jmpb#eb] jump ebb12