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[AArch64] Merge Fcmp32 and Fcmp64 (#4032)

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Copyright (c) 2022, Arm Limited.
This commit is contained in:
Sam Parker
2022-04-14 23:39:43 +01:00
committed by GitHub
parent a40b5c3985
commit cf533a8041
8 changed files with 202 additions and 220 deletions
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9
cranelift/codegen/src/isa/aarch64/inst/emit.rs
View File

@@ -2008,15 +2008,10 @@ impl MachInstEmit for Inst {
assert_eq!(machreg_to_vec(rn2), (machreg_to_vec(rn) + 1) % 32);
sink.put4(enc_tbl(is_extension, 0b01, rd, rn, rm));
}
&Inst::FpuCmp32 { rn, rm } => {
&Inst::FpuCmp { size, rn, rm } => {
let rn = allocs.next(rn);
let rm = allocs.next(rm);
sink.put4(enc_fcmp(ScalarSize::Size32, rn, rm));
}
&Inst::FpuCmp64 { rn, rm } => {
let rn = allocs.next(rn);
let rm = allocs.next(rm);
sink.put4(enc_fcmp(ScalarSize::Size64, rn, rm));
sink.put4(enc_fcmp(size, rn, rm));
}
&Inst::FpuToInt { op, rd, rn } => {
let rd = allocs.next_writable(rd);

6
cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
View File

@@ -5821,7 +5821,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::FpuCmp32 {
Inst::FpuCmp {
size: ScalarSize::Size32,
rn: vreg(23),
rm: vreg(24),
},
@@ -5830,7 +5831,8 @@ fn test_aarch64_binemit() {
));
insns.push((
Inst::FpuCmp64 {
Inst::FpuCmp {
size: ScalarSize::Size64,
rn: vreg(23),
rm: vreg(24),
},

13
cranelift/codegen/src/isa/aarch64/inst/mod.rs
View File

@@ -807,7 +807,7 @@ fn aarch64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
collector.reg_use(rn);
collector.reg_use(rm);
}
&Inst::FpuCmp32 { rn, rm } | &Inst::FpuCmp64 { rn, rm } => {
&Inst::FpuCmp { rn, rm, .. } => {
collector.reg_use(rn);
collector.reg_use(rm);
}
@@ -1765,14 +1765,9 @@ impl Inst {
let ra = pretty_print_vreg_scalar(ra, size, allocs);
format!("{} {}, {}, {}, {}", op, rd, rn, rm, ra)
}
&Inst::FpuCmp32 { rn, rm } => {
let rn = pretty_print_vreg_scalar(rn, ScalarSize::Size32, allocs);
let rm = pretty_print_vreg_scalar(rm, ScalarSize::Size32, allocs);
format!("fcmp {}, {}", rn, rm)
}
&Inst::FpuCmp64 { rn, rm } => {
let rn = pretty_print_vreg_scalar(rn, ScalarSize::Size64, allocs);
let rm = pretty_print_vreg_scalar(rm, ScalarSize::Size64, allocs);
&Inst::FpuCmp { size, rn, rm } => {
let rn = pretty_print_vreg_scalar(rn, size, allocs);
let rm = pretty_print_vreg_scalar(rm, size, allocs);
format!("fcmp {}, {}", rn, rm)
}
&Inst::FpuLoad32 { rd, ref mem, .. } => {