s390x: Refactor branch and jumptable emission
The BranchTarget abstraction is no longer needed, since all branches are being emitted using a MachLabel target. Remove BranchTarget and simply use MachLabel everywhere a branch target is required. (This brings the s390x back-end in line with what x64 does as well.) In addition, simplify jumptable emission by moving all instructions that do not depend on the internal label (i.e. the conditional branch to the default label, as well as the scaling the index register) out of the combined JTSequence instruction. This refactoring will make moving branch generation to ISLE easier.
This commit is contained in:
Ulrich Weigand
@@ -1,7 +1,6 @@
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//! S390x ISA: binary code emission.
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use crate::binemit::{Reloc, StackMap};
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use crate::ir::condcodes::IntCC;
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use crate::ir::MemFlags;
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use crate::ir::{SourceLoc, TrapCode};
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use crate::isa::s390x::inst::*;
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@@ -153,14 +152,9 @@ pub fn mem_emit(
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&enc_rxy(opcode_rxy.unwrap(), rd, base, index, disp.bits()),
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);
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}
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&MemArg::Label { ref target } => {
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if let Some(l) = target.as_label() {
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sink.use_label_at_offset(sink.cur_offset(), l, LabelUse::BranchRIL);
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}
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put(
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sink,
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&enc_ril_b(opcode_ril.unwrap(), rd, target.as_ril_offset_or_zero()),
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);
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&MemArg::Label { target } => {
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sink.use_label_at_offset(sink.cur_offset(), target, LabelUse::BranchRIL);
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put(sink, &enc_ril_b(opcode_ril.unwrap(), rd, 0));
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}
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&MemArg::Symbol {
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ref name, offset, ..
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@@ -1904,60 +1898,43 @@ impl MachInstEmit for Inst {
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&Inst::EpiloguePlaceholder => {
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// Noop; this is just a placeholder for epilogues.
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}
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&Inst::Jump { ref dest } => {
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&Inst::Jump { dest } => {
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let off = sink.cur_offset();
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// Indicate that the jump uses a label, if so, so that a fixup can occur later.
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if let Some(l) = dest.as_label() {
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sink.use_label_at_offset(off, l, LabelUse::BranchRIL);
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sink.add_uncond_branch(off, off + 6, l);
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}
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sink.use_label_at_offset(off, dest, LabelUse::BranchRIL);
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sink.add_uncond_branch(off, off + 6, dest);
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// Emit the jump itself.
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let opcode = 0xc04; // BCRL
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put(sink, &enc_ril_c(opcode, 15, dest.as_ril_offset_or_zero()));
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put(sink, &enc_ril_c(opcode, 15, 0));
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}
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&Inst::IndirectBr { rn, .. } => {
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let opcode = 0x07; // BCR
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put(sink, &enc_rr(opcode, gpr(15), rn));
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}
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&Inst::CondBr {
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ref taken,
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ref not_taken,
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taken,
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not_taken,
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cond,
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} => {
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let opcode = 0xc04; // BCRL
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// Conditional part first.
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let cond_off = sink.cur_offset();
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if let Some(l) = taken.as_label() {
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sink.use_label_at_offset(cond_off, l, LabelUse::BranchRIL);
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let inverted = &enc_ril_c(opcode, cond.invert().bits(), 0);
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sink.add_cond_branch(cond_off, cond_off + 6, l, inverted);
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}
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put(
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sink,
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&enc_ril_c(opcode, cond.bits(), taken.as_ril_offset_or_zero()),
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);
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sink.use_label_at_offset(cond_off, taken, LabelUse::BranchRIL);
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let inverted = &enc_ril_c(opcode, cond.invert().bits(), 0);
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sink.add_cond_branch(cond_off, cond_off + 6, taken, inverted);
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put(sink, &enc_ril_c(opcode, cond.bits(), 0));
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// Unconditional part next.
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let uncond_off = sink.cur_offset();
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if let Some(l) = not_taken.as_label() {
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sink.use_label_at_offset(uncond_off, l, LabelUse::BranchRIL);
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sink.add_uncond_branch(uncond_off, uncond_off + 6, l);
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}
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put(
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sink,
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&enc_ril_c(opcode, 15, not_taken.as_ril_offset_or_zero()),
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);
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sink.use_label_at_offset(uncond_off, not_taken, LabelUse::BranchRIL);
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sink.add_uncond_branch(uncond_off, uncond_off + 6, not_taken);
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put(sink, &enc_ril_c(opcode, 15, 0));
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}
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&Inst::OneWayCondBr { ref target, cond } => {
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&Inst::OneWayCondBr { target, cond } => {
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let opcode = 0xc04; // BCRL
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if let Some(l) = target.as_label() {
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sink.use_label_at_offset(sink.cur_offset(), l, LabelUse::BranchRIL);
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}
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put(
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sink,
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&enc_ril_c(opcode, cond.bits(), target.as_ril_offset_or_zero()),
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);
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sink.use_label_at_offset(sink.cur_offset(), target, LabelUse::BranchRIL);
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put(sink, &enc_ril_c(opcode, cond.bits(), 0));
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}
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&Inst::Nop0 => {}
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&Inst::Nop2 => {
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@@ -1984,86 +1961,49 @@ impl MachInstEmit for Inst {
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let srcloc = state.cur_srcloc();
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put_with_trap(sink, &enc_e(0x0000), srcloc, trap_code);
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}
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&Inst::JTSequence {
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ridx,
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rtmp1,
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rtmp2,
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ref info,
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..
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} => {
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&Inst::JTSequence { ridx, ref targets } => {
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let table_label = sink.get_label();
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// This sequence is *one* instruction in the vcode, and is expanded only here at
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// emission time, because we cannot allow the regalloc to insert spills/reloads in
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// the middle; we depend on hardcoded PC-rel addressing below.
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// Bounds-check index and branch to default.
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let inst = Inst::CmpRUImm32 {
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op: CmpOp::CmpL64,
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rn: ridx,
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imm: info.targets.len() as u32,
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};
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inst.emit(sink, emit_info, state);
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let inst = Inst::OneWayCondBr {
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target: info.default_target,
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cond: Cond::from_intcc(IntCC::UnsignedGreaterThanOrEqual),
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};
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inst.emit(sink, emit_info, state);
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// Set rtmp2 to index scaled by entry size.
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let inst = Inst::ShiftRR {
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shift_op: ShiftOp::LShL64,
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rd: rtmp2,
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rn: ridx,
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shift_imm: 2,
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shift_reg: zero_reg(),
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};
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inst.emit(sink, emit_info, state);
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// Set rtmp1 to address of jump table.
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// Set temp register to address of jump table.
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let rtmp = writable_spilltmp_reg();
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let inst = Inst::LoadAddr {
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rd: rtmp1,
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rd: rtmp,
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mem: MemArg::Label {
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target: BranchTarget::Label(table_label),
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target: table_label,
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},
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};
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inst.emit(sink, emit_info, state);
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// Set rtmp2 to value loaded out of jump table.
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let inst = Inst::Load64SExt32 {
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rd: rtmp2,
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mem: MemArg::reg_plus_reg(rtmp1.to_reg(), rtmp2.to_reg(), MemFlags::trusted()),
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};
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inst.emit(sink, emit_info, state);
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// Set rtmp1 to target address (rtmp1 + rtmp2).
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let inst = Inst::AluRRR {
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alu_op: ALUOp::Add64,
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rd: rtmp1,
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rn: rtmp1.to_reg(),
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rm: rtmp2.to_reg(),
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// Set temp to target address by adding the value of the jump table entry.
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let inst = Inst::AluRX {
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alu_op: ALUOp::Add64Ext32,
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rd: rtmp,
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mem: MemArg::reg_plus_reg(rtmp.to_reg(), ridx, MemFlags::trusted()),
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};
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inst.emit(sink, emit_info, state);
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// Branch to computed address. (`targets` here is only used for successor queries
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// and is not needed for emission.)
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let inst = Inst::IndirectBr {
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rn: rtmp1.to_reg(),
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rn: rtmp.to_reg(),
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targets: vec![],
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};
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inst.emit(sink, emit_info, state);
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// Emit jump table (table of 32-bit offsets).
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// The first entry is the default target, which is not emitted
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// into the jump table, so we skip it here. It is only in the
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// list so MachTerminator will see the potential target.
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sink.bind_label(table_label);
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let jt_off = sink.cur_offset();
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for &target in info.targets.iter() {
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for &target in targets.iter().skip(1) {
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let word_off = sink.cur_offset();
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let off_into_table = word_off - jt_off;
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sink.use_label_at_offset(
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word_off,
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target.as_label().unwrap(),
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LabelUse::PCRel32,
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);
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sink.use_label_at_offset(word_off, target, LabelUse::PCRel32);
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sink.put4(off_into_table.swap_bytes());
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}
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