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Fix up adjust_sp_imm instruction.

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* Use imm64 rather than offset32
* Add predicate to enforce signed 32-bit limit to imm
* Remove AdjustSpImm format
* Add encoding tests for adjust_sp_imm
* Adjust use of adjust_sp_imm in Intel prologue_epilogue to match
This commit is contained in:
Tyler McMullen
2017-12-02 15:37:04 -08:00
committed by Jakob Stoklund Olesen
parent 1a11c351b5
commit ced39f5186
11 changed files with 46 additions and 27 deletions
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9
lib/cretonne/meta/isa/intel/recipes.py
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@@ -10,7 +10,7 @@ from base.formats import Trap, Call, IndirectCall, Store, Load
from base.formats import IntCompare, FloatCompare, IntCond, FloatCond
from base.formats import Jump, Branch, BranchInt, BranchFloat
from base.formats import Ternary, FuncAddr, UnaryGlobalVar
from base.formats import RegMove, RegSpill, RegFill, CopySpecial, AdjustSpImm
from base.formats import RegMove, RegSpill, RegFill, CopySpecial
from .registers import GPR, ABCD, FPR, GPR8, FPR8, FLAG, StackGPR32, StackFPR32
from .defs import supported_floatccs
@@ -494,12 +494,13 @@ copysp = TailRecipe(
''')
adjustsp = TailRecipe(
'adjustsp', AdjustSpImm, size=5, ins=(), outs=(),
'adjustsp', UnaryImm, size=5, ins=(), outs=(),
instp=IsSignedInt(UnaryImm.imm, 32),
emit='''
PUT_OP(bits, rex1(4), sink);
modrm_r_bits(4, bits, sink);
let offset: i32 = offset.into();
sink.put4(offset as u32);
let imm: i64 = imm.into();
sink.put4(imm as u32);
''')