[build] Remove dead code in Python and move assertions to the Rust code generator;

lib/codegen/meta-python/cdsl/isa.py

@@ -48,7 +48,6 @@ class TargetISA(object):
         self.instruction_groups = instruction_groups
         self.cpumodes = list()  # type: List[CPUMode]
         self.regbanks = list()  # type: List[RegBank]
-        self.regclasses = list()  # type: List[RegClass]
         self.legalize_codes = OrderedDict()  # type: OrderedDict[XFormGroup, int]  # noqa
         # Unique copies of all predicates.
         self._predicates = dict()  # type: Dict[PredKey, PredNode]
@@ -74,7 +73,6 @@ class TargetISA(object):
         """
         self._collect_encoding_recipes()
         self._collect_predicates()
-        self._collect_regclasses()
         self._collect_legalize_codes()
         return self
 
@@ -122,49 +120,6 @@ class TargetISA(object):
                 if enc.isap:
                     self.settings.number_predicate(enc.isap)
 
-    def _collect_regclasses(self):
-        # type: () -> None
-        """
-        Collect and number register classes.
-
-        Every register class needs a unique index, and the classes need to be
-        topologically ordered.
-
-        We also want all the top-level register classes to be first.
-        """
-        # Compute subclasses and top-level classes in each bank.
-        # Collect the top-level classes so they get numbered consecutively.
-        for bank in self.regbanks:
-            bank.finish_regclasses()
-            # Always get the pressure tracking classes in first.
-            if bank.pressure_tracking:
-                self.regclasses.extend(bank.toprcs)
-
-        # The limit on the number of top-level register classes can be raised.
-        # This should be coordinated with the `MAX_TRACKED_TOPRCS` constant in
-        # `isa/registers.rs`.
-        assert len(self.regclasses) <= 4, "Too many top-level register classes"
-
-        # Get the remaining top-level register classes which may exceed
-        # `MAX_TRACKED_TOPRCS`.
-        for bank in self.regbanks:
-            if not bank.pressure_tracking:
-                self.regclasses.extend(bank.toprcs)
-
-        # Collect all of the non-top-level register classes.
-        # They are numbered strictly after the top-level classes.
-        for bank in self.regbanks:
-            self.regclasses.extend(
-                    rc for rc in bank.classes if not rc.is_toprc())
-
-        for idx, rc in enumerate(self.regclasses):
-            rc.index = idx
-
-        # The limit on the number of register classes can be changed. It should
-        # be coordinated with the `RegClassMask` and `RegClassIndex` types in
-        # `isa/registers.rs`.
-        assert len(self.regclasses) <= 32, "Too many register classes"
-
     def _collect_legalize_codes(self):
         # type: () -> None
         """

lib/codegen/meta/src/cdsl/isa.rs

@@ -165,6 +165,25 @@ impl TargetIsaBuilder {
             }
         }
 
+        // This limit should be coordinated with the `RegClassMask` and `RegClassIndex` types in
+        // isa/registers.rs of the non-meta code.
+        assert!(
+            self.isa.reg_classes.len() <= 32,
+            "Too many register classes"
+        );
+
+        // The maximum number of top-level register classes which have pressure tracking should be
+        // kept in sync with the MAX_TRACKED_TOPRCS constant in isa/registers.rs of the non-meta
+        // code.
+        let num_toplevel = self
+            .isa
+            .reg_classes
+            .values()
+            .filter(|x| {
+                x.toprc == x.index && self.isa.reg_banks.get(x.bank).unwrap().pressure_tracking
+            }).count();
+        assert!(num_toplevel <= 4, "Too many top-level register classes");
+
         self.isa
     }
 }