add riscv64 backend for cranelift. (#4271)

Add a RISC-V 64 (`riscv64`, RV64GC) backend.

Co-authored-by: yuyang <756445638@qq.com>
Co-authored-by: Chris Fallin <chris@cfallin.org>
Co-authored-by: Afonso Bordado <afonsobordado@az8.co>

tests/all/memory.rs

@@ -19,7 +19,7 @@ fn module(engine: &Engine) -> Result<Module> {
             (2, &["i32.load16_s"]),
             (4, &["i32.load" /*, "f32.load"*/]),
             (8, &["i64.load" /*, "f64.load"*/]),
-            #[cfg(not(target_arch = "s390x"))]
+            #[cfg(not(any(target_arch = "s390x", target_arch = "riscv64")))]
             (16, &["v128.load"]),
         ]
         .iter()

tests/host_segfault.rs

@@ -144,6 +144,10 @@ fn main() {
             },
             true,
         ),
+        #[cfg(not(any(target_arch = "riscv64")))]
+        // Due to `InstanceAllocationStrategy::pooling()` trying to alloc more than 6000G memory space.
+        // https://gitlab.com/qemu-project/qemu/-/issues/1214
+        // https://gitlab.com/qemu-project/qemu/-/issues/290
         (
             "hit async stack guard page with pooling allocator",
             || {