add riscv64 backend for cranelift. (#4271)

Add a RISC-V 64 (`riscv64`, RV64GC) backend.

Co-authored-by: yuyang <756445638@qq.com>
Co-authored-by: Chris Fallin <chris@cfallin.org>
Co-authored-by: Afonso Bordado <afonsobordado@az8.co>

cranelift/filetests/filetests/runtests/div-checks.clif

@@ -3,6 +3,8 @@ set avoid_div_traps=false
 target aarch64
 target s390x
 target x86_64
+target riscv64 
+
 
 ; Tests that the `avoid_div_traps` flag prevents a trap when {s,u}rem is called
 ; with INT_MIN % -1.