add riscv64 backend for cranelift. (#4271)

Add a RISC-V 64 (`riscv64`, RV64GC) backend.

Co-authored-by: yuyang <756445638@qq.com>
Co-authored-by: Chris Fallin <chris@cfallin.org>
Co-authored-by: Afonso Bordado <afonsobordado@az8.co>

cranelift/filetests/filetests/runtests/ceil.clif

@@ -4,6 +4,7 @@ target x86_64
 target x86_64 has_sse41=false
 target aarch64
 target s390x
+target riscv64
 
 function %ceil_f32(f32) -> f32 {
 block0(v0: f32):