add riscv64 backend for cranelift. (#4271)
Add a RISC-V 64 (`riscv64`, RV64GC) backend. Co-authored-by: yuyang <756445638@qq.com> Co-authored-by: Chris Fallin <chris@cfallin.org> Co-authored-by: Afonso Bordado <afonsobordado@az8.co>
This commit is contained in:
yuyang-ok
983
cranelift/codegen/src/isa/riscv64/lower.isle
Normal file
983
cranelift/codegen/src/isa/riscv64/lower.isle
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@@ -0,0 +1,983 @@
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;; riscv64 instruction selection and CLIF-to-MachInst lowering.
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;; The main lowering constructor term: takes a clif `Inst` and returns the
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;; register(s) within which the lowered instruction's result values live.
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(decl lower (Inst) InstOutput)
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;;;; Rules for `iconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty (iconst (u64_from_imm64 n))))
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(imm ty n))
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;;;; Rules for `bconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty (bconst $false)))
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(imm ty 0))
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(rule (lower (has_type ty (bconst $true)))
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(imm ty 1))
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;;;; Rules for `null` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty (null)))
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(imm ty 0))
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;;;; Rules for `iadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (fits_in_32 ty) (iadd x y)))
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(alu_rrr (AluOPRRR.Addw) x y))
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;; Base case, simply adding things in registers.
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(rule (lower (has_type (fits_in_64 ty) (iadd x y)))
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(alu_add x y))
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;; Special cases for when one operand is an immediate that fits in 12 bits.
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(rule (lower (has_type (fits_in_64 ty) (iadd x (imm12_from_value y))))
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(alu_rr_imm12 (select_addi ty) x y))
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(rule (lower (has_type (fits_in_64 ty) (iadd (imm12_from_value x) y)))
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(alu_rr_imm12 (select_addi ty) y x))
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(rule
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(lower (has_type $I128 (iadd x y)))
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(let
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( ;; low part.
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(low Reg (alu_add (value_regs_get x 0) (value_regs_get y 0)))
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;; compute carry.
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(carry Reg(alu_rrr (AluOPRRR.SltU) low (value_regs_get y 0)))
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;;
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(high_tmp Reg (alu_add (value_regs_get x 1) (value_regs_get y 1)))
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;; add carry.
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(high Reg (alu_add high_tmp carry)))
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(value_regs low high)))
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;;; Rules for `iadd_ifcout` ;;;;;;;;;;;;;
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(rule
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(lower (has_type (fits_in_64 ty) (iadd_ifcout x y)))
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(output_ifcout (alu_add x y)))
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;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Base case, simply subtracting things in registers.
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(rule (lower (has_type (fits_in_64 ty) (isub x y)))
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(alu_rrr (AluOPRRR.Sub) x y))
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(rule (lower (has_type (fits_in_32 ty) (isub x y)))
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(alu_rrr (AluOPRRR.Subw) x y))
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(rule (lower (has_type $I128 (isub x y)))
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(i128_sub x y))
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;;;; Rules for `ineg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; `i64` and smaller.
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(rule (lower (has_type (fits_in_64 ty) (ineg x)))
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(alu_rrr (AluOPRRR.Sub) (zero_reg) x))
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;;;; Rules for `imul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (fits_in_64 ty) (imul x y)))
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(alu_rrr (AluOPRRR.Mul) x y))
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(rule (lower (has_type (fits_in_32 ty) (imul x y)))
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(alu_rrr (AluOPRRR.Mulw) x y))
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;;;; Rules for `smulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (fits_in_64 ty) (smulhi x y)))
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(lower_smlhi ty (ext_int_if_need $true x ty) (ext_int_if_need $true y ty)))
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;;;; Rules for `umulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (fits_in_64 ty) (umulhi x y)))
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(lower_umlhi ty (ext_int_if_need $false x ty) (ext_int_if_need $false y ty)))
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;; for I128
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(rule (lower (has_type $I128 (imul x y)))
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(let
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((x_regs ValueRegs x)
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(x_lo Reg (value_regs_get x_regs 0))
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(x_hi Reg (value_regs_get x_regs 1))
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;; Get the high/low registers for `y`.
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(y_regs ValueRegs y)
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(y_lo Reg (value_regs_get y_regs 0))
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(y_hi Reg (value_regs_get y_regs 1))
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;; 128bit mul formula:
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;; dst_lo = x_lo * y_lo
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;; dst_hi = umulhi(x_lo, y_lo) + (x_lo * y_hi) + (x_hi * y_lo)
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;;
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;; We can convert the above formula into the following
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;; umulh dst_hi, x_lo, y_lo
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;; madd dst_hi, x_lo, y_hi, dst_hi
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;; madd dst_hi, x_hi, y_lo, dst_hi
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;; madd dst_lo, x_lo, y_lo, zero
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(dst_hi1 Reg (umulh x_lo y_lo))
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(dst_hi2 Reg (madd x_lo y_hi dst_hi1))
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(dst_hi Reg (madd x_hi y_lo dst_hi2))
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(dst_lo Reg (madd x_lo y_lo (zero_reg))))
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(value_regs dst_lo dst_hi)))
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;;;; Rules for `div` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (fits_in_32 ty) (udiv x y)))
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(let
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((y2 Reg (ext_int_if_need $false y ty))
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(_ InstOutput (gen_div_by_zero y2)))
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(alu_rrr (AluOPRRR.Divuw) (ext_int_if_need $false x ty) y2)))
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(rule (lower (has_type (fits_in_32 ty) (sdiv x y)))
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(let
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((a Reg (ext_int_if_need $true x ty))
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(b Reg (ext_int_if_need $true y ty))
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(_ InstOutput (gen_div_overflow a b ty))
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(_ InstOutput (gen_div_by_zero b)))
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(alu_rrr (AluOPRRR.Divw) a b)))
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(rule (lower (has_type $I64 (sdiv x y)))
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(let
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((_ InstOutput (gen_div_overflow x y $I64))
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(_ InstOutput (gen_div_by_zero y)) )
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(alu_rrr (AluOPRRR.Div) x y)))
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(rule (lower (has_type $I64 (udiv x y)))
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(let
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((_ InstOutput (gen_div_by_zero y)))
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(alu_rrr (AluOPRRR.DivU) x y)))
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;;;; Rules for `rem` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (fits_in_16 ty) (urem x y)))
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(let
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((y2 Reg(ext_int_if_need $false y ty))
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(_ InstOutput (gen_div_by_zero y2)))
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(alu_rrr (AluOPRRR.Remuw) (ext_int_if_need $false x ty) y2)))
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(rule (lower (has_type (fits_in_16 ty) (srem x y)))
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(let
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((y2 Reg (ext_int_if_need $true y ty))
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(_ InstOutput (gen_div_by_zero y2)))
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(alu_rrr (AluOPRRR.Remw) (ext_int_if_need $true x ty) y2)))
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(rule (lower (has_type $I32 (srem x y)))
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(let
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((y2 Reg (ext_int_if_need $true y $I32))
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(_ InstOutput (gen_div_by_zero y2)))
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(alu_rrr (AluOPRRR.Remw) x y2)))
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(rule (lower (has_type $I32 (urem x y)))
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(let
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((y2 Reg (ext_int_if_need $false y $I32))
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(_ InstOutput (gen_div_by_zero y2)))
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(alu_rrr (AluOPRRR.Remuw) x y2)))
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(rule (lower (has_type $I64 (srem x y)))
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(let
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((_ InstOutput (gen_div_by_zero y)))
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(alu_rrr (AluOPRRR.Rem) x y)))
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(rule (lower (has_type $I64 (urem x y)))
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(let
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((_ InstOutput (gen_div_by_zero y)))
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(alu_rrr (AluOPRRR.RemU) x y)))
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;;;; Rules for `and` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (fits_in_64 ty) (band x y)))
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(alu_rrr (AluOPRRR.And) x y))
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;; Special cases for when one operand is an immediate that fits in 12 bits.
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(rule (lower (has_type (fits_in_64 ty) (band x (imm12_from_value y))))
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(alu_rr_imm12 (AluOPRRI.Andi) x y))
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(rule (lower (has_type (fits_in_64 ty) (band (imm12_from_value x) y)))
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(alu_rr_imm12 (AluOPRRI.Andi) y x))
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(rule (lower (has_type $B128 (band x y)))
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(lower_b128_binary (AluOPRRR.And) x y))
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(rule (lower (has_type $I128 (band x y)))
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(lower_b128_binary (AluOPRRR.And) x y))
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(rule (lower (has_type $F32 (band x y)))
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(lower_float_binary (AluOPRRR.And) x y $F32))
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(rule (lower (has_type $F64 (band x y)))
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(lower_float_binary (AluOPRRR.And) x y $F64))
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;;;; Rules for `or` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (fits_in_64 ty) (bor x y)))
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(alu_rrr (AluOPRRR.Or) x y))
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;; Special cases for when one operand is an immediate that fits in 12 bits.
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(rule (lower (has_type (fits_in_64 ty) (bor x (imm12_from_value y))))
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(alu_rr_imm12 (AluOPRRI.Ori) x y))
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(rule (lower (has_type (fits_in_64 ty) (bor (imm12_from_value x) y)))
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(alu_rr_imm12 (AluOPRRI.Ori) y x))
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(rule (lower (has_type $B128 (bor x y)))
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(lower_b128_binary (AluOPRRR.Or) x y))
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(rule (lower (has_type $I128 (bor x y)))
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(lower_b128_binary (AluOPRRR.Or) x y))
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(rule (lower (has_type $F32 (bor x y)))
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(lower_float_binary (AluOPRRR.Or) x y $F32))
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(rule (lower (has_type $F64 (bor x y)))
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(lower_float_binary (AluOPRRR.Or) x y $F64))
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;;;; Rules for `xor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (fits_in_64 ty) (bxor x y)))
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(alu_rrr (AluOPRRR.Xor) x y))
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;; Special cases for when one operand is an immediate that fits in 12 bits.
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(rule (lower (has_type (fits_in_64 ty) (bxor x (imm12_from_value y))))
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(alu_rr_imm12 (AluOPRRI.Xori) x y))
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(rule (lower (has_type (fits_in_64 ty) (bxor (imm12_from_value x) y)))
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(alu_rr_imm12 (AluOPRRI.Xori) y x))
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(rule (lower (has_type $B128 (bxor x y)))
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(lower_b128_binary (AluOPRRR.Xor) x y))
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(rule (lower (has_type $I128 (bxor x y)))
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(lower_b128_binary (AluOPRRR.Xor) x y))
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(rule (lower (has_type $F32 (bxor x y)))
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(lower_float_binary (AluOPRRR.Xor) x y $F32))
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(rule (lower (has_type $F64 (bxor x y)))
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(lower_float_binary (AluOPRRR.Xor) x y $F64))
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;;;; Rules for `bnot` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type fits_in_64 (bnot x)))
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(alu_rr_imm12 (AluOPRRI.Xori) x (imm_from_neg_bits -1)))
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(rule (lower (has_type $I128 (bnot x)))
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(bnot_128 x))
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(rule (lower (has_type $B128 (bnot x)))
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(bnot_128 x))
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(rule
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(lower (has_type $F32 (bnot x)))
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(lower_float_bnot x $F32)
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)
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(rule
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(lower (has_type $F64 (bnot x)))
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(lower_float_bnot x $F64)
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)
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;;;; Rules for `bit_reverse` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty (bitrev x)))
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(lower_bit_reverse x ty))
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(rule (lower (has_type $I128 (bitrev x)))
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(let ((val ValueRegs x)
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(lo_rev Reg (lower_bit_reverse (value_regs_get val 0) $I64))
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(hi_rev Reg (lower_bit_reverse (value_regs_get val 1) $I64)))
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(value_regs hi_rev lo_rev)))
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;;;; Rules for `ctz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty (ctz x)))
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(lower_ctz ty x))
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(rule (lower (has_type $I128 (ctz x)))
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(lower_ctz_128 x))
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;;;; Rules for `clz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty (clz x)))
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(lower_clz ty x))
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(rule (lower (has_type $I128 (clz x)))
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(lower_clz_i128 x))
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;;;; Rules for `uextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type out (uextend x @ (value_type in))))
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(lower_extend x $false (ty_bits in) (ty_bits out)))
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;;;; Rules for `sextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type out (sextend x @ (value_type in))))
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(lower_extend x $true (ty_bits in) (ty_bits out)))
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;;;; Rules for `band_not` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (fits_in_64 ty) (band_not x y)))
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(gen_andn x y))
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(rule (lower (has_type $I128 (band_not x y)))
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(let
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((low Reg (gen_andn (value_regs_get x 0) (value_regs_get y 0)))
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(high Reg (gen_andn (value_regs_get x 1) (value_regs_get y 1))))
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(value_regs low high)))
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;;;; Rules for `popcnt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (fits_in_64 ty) (popcnt x)))
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(lower_popcnt x ty))
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(rule (lower (has_type $I128 (popcnt x)))
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(lower_popcnt_i128 x))
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;;;; Rules for `ishl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type $I8 (ishl x (valueregs_2_reg y))))
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(alu_rrr (AluOPRRR.Sllw) x (alu_andi y 7))
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)
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(rule (lower (has_type $I8(ishl x (imm12_from_value y))))
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(alu_rr_imm12 (AluOPRRI.Slliw) x (imm12_and y 7)))
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(rule (lower (has_type $I16 (ishl x (valueregs_2_reg y))))
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(alu_rrr (AluOPRRR.Sllw) x (alu_andi y 15))
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)
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(rule (lower (has_type $I16(ishl x (imm12_from_value y))))
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(alu_rr_imm12 (AluOPRRI.Slliw) x (imm12_and y 15)))
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(rule (lower (has_type $I32(ishl x (valueregs_2_reg y))))
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(alu_rrr (AluOPRRR.Sllw) x y))
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(rule (lower (has_type $I32 (ishl x (imm12_from_value y))))
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(alu_rr_imm12 (AluOPRRI.Slliw) x y))
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(rule (lower (has_type $I64 (ishl x (imm12_from_value y))))
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(alu_rr_imm12 (AluOPRRI.Slli) x y))
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(rule (lower (has_type $I64(ishl x (valueregs_2_reg y))))
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(alu_rrr (AluOPRRR.Sll) x y))
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(rule (lower (has_type $I128 (ishl x y)))
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(lower_i128_ishl x y))
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;;;; Rules for `ushr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type $I8 (ushr x (valueregs_2_reg y))))
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(alu_rrr (AluOPRRR.Srlw) (ext_int_if_need $false x $I8) (alu_andi y 7))
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)
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(rule (lower (has_type $I8(ushr x (imm12_from_value y))))
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(alu_rr_imm12 (AluOPRRI.SrliW) (ext_int_if_need $false x $I8) (imm12_and y 7)))
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(rule (lower (has_type $I16 (ushr x (valueregs_2_reg y))))
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(alu_rrr (AluOPRRR.Srlw) (ext_int_if_need $false x $I16) (alu_andi y 15))
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)
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(rule (lower (has_type $I16(ushr x (imm12_from_value y))))
|
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(alu_rr_imm12 (AluOPRRI.SrliW) (ext_int_if_need $false x $I16) (imm12_and y 15)))
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||||
|
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(rule (lower (has_type $I32(ushr x (valueregs_2_reg y))))
|
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(alu_rrr (AluOPRRR.Srlw) x y))
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(rule (lower (has_type $I32 (ushr x (imm12_from_value y))))
|
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(alu_rr_imm12 (AluOPRRI.SrliW) x y))
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|
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(rule (lower (has_type $I64 (ushr x (imm12_from_value y))))
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(alu_rr_imm12 (AluOPRRI.Srli) x y))
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||||
(rule (lower (has_type $I64(ushr x (valueregs_2_reg y))))
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(alu_rrr (AluOPRRR.Srl) x y))
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||||
|
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(rule (lower (has_type $I128 (ushr x y)))
|
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(lower_i128_ushr x y))
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||||
|
||||
|
||||
;;;; Rules for `sshr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
(rule (lower (has_type $I8 (sshr x (valueregs_2_reg y))))
|
||||
(alu_rrr (AluOPRRR.Sra) (ext_int_if_need $true x $I8) (alu_andi y 7))
|
||||
)
|
||||
(rule (lower (has_type $I8(sshr x (imm12_from_value y))))
|
||||
(alu_rr_imm12 (AluOPRRI.Srai) (ext_int_if_need $true x $I8) (imm12_and y 7)))
|
||||
|
||||
(rule (lower (has_type $I16 (sshr x (valueregs_2_reg y))))
|
||||
(alu_rrr (AluOPRRR.Sra) (ext_int_if_need $true x $I16) (alu_andi y 15))
|
||||
)
|
||||
(rule (lower (has_type $I16(sshr x (imm12_from_value y))))
|
||||
(alu_rr_imm12 (AluOPRRI.Srai) (ext_int_if_need $true x $I16) (imm12_and y 15)))
|
||||
|
||||
(rule (lower (has_type $I32 (sshr x (valueregs_2_reg y))))
|
||||
(alu_rrr (AluOPRRR.Sraw) x y))
|
||||
(rule (lower (has_type $I32 (sshr x (imm12_from_value y))))
|
||||
(alu_rr_imm12 (AluOPRRI.Sraiw) x y))
|
||||
(rule (lower (has_type $I64 (sshr x (valueregs_2_reg y))))
|
||||
(alu_rrr (AluOPRRR.Sra) x y))
|
||||
(rule (lower (has_type $I64(sshr x (imm12_from_value y))))
|
||||
(alu_rr_imm12 (AluOPRRI.Srai) x y))
|
||||
(rule (lower (has_type $I128 (sshr x y)))
|
||||
(lower_i128_sshr x y))
|
||||
|
||||
|
||||
;;;; Rules for `rotl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
(rule (lower (has_type (fits_in_64 ty)(rotl x (valueregs_2_reg y))))
|
||||
(lower_rotl ty (ext_int_if_need $false x ty) y))
|
||||
|
||||
(rule (lower (has_type $I128 (rotl x y)))
|
||||
(lower_i128_rotl x y))
|
||||
|
||||
;;;; Rules for `rotr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
(rule (lower (has_type (fits_in_64 ty)(rotr x (valueregs_2_reg y))))
|
||||
(lower_rotr ty (ext_int_if_need $false x ty) y))
|
||||
|
||||
(rule (lower (has_type $I128 (rotr x y)))
|
||||
(lower_i128_rotr x y))
|
||||
|
||||
|
||||
;;;; Rules for `bxor_not` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; notice x y order!!!
|
||||
(rule (lower (has_type (fits_in_64 ty)(bxor_not x y)))
|
||||
(gen_xor_not x y))
|
||||
(rule (lower (has_type $I128 (bxor_not x y)))
|
||||
(let
|
||||
((low Reg (gen_xor_not (value_regs_get x 0) (value_regs_get y 0)))
|
||||
(high Reg (gen_xor_not (value_regs_get x 1) (value_regs_get y 1))))
|
||||
(value_regs low high)
|
||||
)
|
||||
)
|
||||
|
||||
;;;; Rules for `bor_not` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
(rule (lower (has_type (fits_in_64 ty)(bor_not x y)))
|
||||
(gen_orn x y))
|
||||
|
||||
(rule (lower (has_type $I128 (bor_not x y)))
|
||||
(let
|
||||
((low Reg (gen_orn (value_regs_get x 0) (value_regs_get y 0)))
|
||||
(high Reg (gen_orn (value_regs_get x 1) (value_regs_get y 1))))
|
||||
(value_regs low high)))
|
||||
|
||||
|
||||
;;;; Rules for `cls` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
(rule (lower (has_type (fits_in_64 ty)(cls x)))
|
||||
(lower_cls x ty))
|
||||
(rule (lower (has_type $I128 (cls x)))
|
||||
(lower_cls_i128 x))
|
||||
|
||||
|
||||
;;;; Rules for `fabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type ty (fabs x)))
|
||||
(gen_fabs x ty))
|
||||
|
||||
;;;; Rules for `fneg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type ty (fneg x)))
|
||||
(fpu_rrr (f_copy_neg_sign_op ty) ty x x))
|
||||
|
||||
;;;; Rules for `fcopysign` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
(rule (lower (has_type ty (fcopysign x y)))
|
||||
(fpu_rrr (f_copysign_op ty) ty x y))
|
||||
|
||||
;;;; Rules for `fma` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
(rule (lower (has_type $F32 (fma x y z)))
|
||||
(fpu_rrrr (FpuOPRRRR.FmaddS) $F64 x y z))
|
||||
(rule (lower (has_type $F64 (fma x y z)))
|
||||
(fpu_rrrr (FpuOPRRRR.FmaddD) $F64 x y z))
|
||||
|
||||
|
||||
;;;; Rules for `sqrt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
(rule (lower (has_type $F32 (sqrt x)))
|
||||
(fpu_rr (FpuOPRR.FsqrtS)$F64 x))
|
||||
|
||||
(rule (lower (has_type $F64 (sqrt x)))
|
||||
(fpu_rr (FpuOPRR.FsqrtD)$F64 x))
|
||||
|
||||
|
||||
;;;; Rules for `AtomicRMW` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
(rule
|
||||
;;
|
||||
(lower
|
||||
(has_type (valid_atomic_transaction ty) (atomic_rmw flags op addr x)))
|
||||
(gen_atomic (get_atomic_rmw_op ty op) addr x (atomic_amo)))
|
||||
|
||||
;;; for I8 and I16
|
||||
(rule
|
||||
(lower
|
||||
(has_type (valid_atomic_transaction (fits_in_16 ty)) (atomic_rmw flags op addr x)))
|
||||
(gen_atomic_rmw_loop op ty addr x))
|
||||
|
||||
;;;special for I8 and I16 max min etc.
|
||||
;;;because I need uextend or sextend the value.
|
||||
(rule
|
||||
(lower
|
||||
(has_type (valid_atomic_transaction (fits_in_16 ty)) (atomic_rmw flags (is_atomic_rmw_max_etc op $true) addr x)))
|
||||
(gen_atomic_rmw_loop op ty addr (ext_int_if_need $true x ty)))
|
||||
|
||||
|
||||
(rule
|
||||
;;
|
||||
(lower
|
||||
(has_type (valid_atomic_transaction (fits_in_16 ty)) (atomic_rmw flags (is_atomic_rmw_max_etc op $false) addr x)))
|
||||
;;
|
||||
(gen_atomic_rmw_loop op ty addr (ext_int_if_need $false x ty)))
|
||||
|
||||
;;;;; Rules for `AtomicRmwOp.Sub`
|
||||
(rule
|
||||
(lower
|
||||
(has_type (valid_atomic_transaction ty) (atomic_rmw flags (AtomicRmwOp.Sub) addr x)))
|
||||
(let
|
||||
((tmp WritableReg (temp_writable_reg ty))
|
||||
(x2 Reg (alu_rrr (AluOPRRR.Sub) (zero_reg) x)))
|
||||
(gen_atomic (get_atomic_rmw_op ty (AtomicRmwOp.Add)) addr x2 (atomic_amo))))
|
||||
|
||||
(decl gen_atomic_rmw_loop (AtomicRmwOp Type Reg Reg) Reg)
|
||||
(rule
|
||||
(gen_atomic_rmw_loop op ty addr x)
|
||||
(let
|
||||
((dst WritableReg (temp_writable_reg $I64))
|
||||
(t0 WritableReg (temp_writable_reg $I64))
|
||||
(_ Unit (emit (MInst.AtomicRmwLoop (gen_atomic_offset addr ty) op dst ty (gen_atomic_p addr ty) x t0))))
|
||||
(writable_reg_to_reg dst)))
|
||||
|
||||
;;;;; Rules for `AtomicRmwOp.Nand`
|
||||
(rule
|
||||
(lower
|
||||
(has_type (valid_atomic_transaction ty) (atomic_rmw flags (AtomicRmwOp.Nand) addr x)))
|
||||
(gen_atomic_rmw_loop (AtomicRmwOp.Nand) ty addr x))
|
||||
|
||||
(decl is_atomic_rmw_max_etc (AtomicRmwOp bool)AtomicRmwOp)
|
||||
(extern extractor is_atomic_rmw_max_etc is_atomic_rmw_max_etc)
|
||||
|
||||
;;;;; Rules for `atomic load`;;;;;;;;;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type (valid_atomic_transaction ty) (atomic_load flags p)))
|
||||
(gen_atomic_load p ty))
|
||||
|
||||
|
||||
;;;;; Rules for `atomic store`;;;;;;;;;;;;;;;;;
|
||||
(rule
|
||||
(lower (atomic_store flags src @ (value_type (valid_atomic_transaction ty)) p))
|
||||
(gen_atomic_store p ty src))
|
||||
|
||||
(decl gen_atomic_offset (Reg Type) Reg)
|
||||
(rule (gen_atomic_offset p (fits_in_16 ty))
|
||||
(alu_slli (alu_andi p 3) 3))
|
||||
|
||||
(rule (gen_atomic_offset p _)
|
||||
(zero_reg))
|
||||
|
||||
(decl gen_atomic_p (Reg Type) Reg)
|
||||
(rule (gen_atomic_p p (fits_in_16 ty))
|
||||
(alu_andi p -4))
|
||||
|
||||
(rule (gen_atomic_p p _)
|
||||
p)
|
||||
|
||||
|
||||
;;;;; Rules for `atomic cas`;;;;;;;;;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type (valid_atomic_transaction ty) (atomic_cas flags p e x)))
|
||||
(let
|
||||
((t0 WritableReg (temp_writable_reg ty))
|
||||
(dst WritableReg (temp_writable_reg ty))
|
||||
(_ Unit(emit (MInst.AtomicCas (gen_atomic_offset p ty) t0 dst (ext_int_if_need $false e ty) (gen_atomic_p p ty) x ty))))
|
||||
(writable_reg_to_reg dst)))
|
||||
|
||||
;;;;; Rules for `copy`;;;;;;;;;;;;;;;;;
|
||||
(rule (lower(has_type ty (copy x)))
|
||||
(gen_move2 x ty ty))
|
||||
|
||||
;;;;; Rules for `breduce`;;;;;;;;;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type ty (breduce x)))
|
||||
(gen_move2 (value_regs_get x 0) ty ty))
|
||||
|
||||
;;;;; Rules for `ireduce`;;;;;;;;;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type ty (ireduce x)))
|
||||
(gen_move2 (value_regs_get x 0) ty ty))
|
||||
|
||||
;;;;; Rules for `fpromote`;;;;;;;;;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type ty (fpromote x)))
|
||||
(fpu_rr (FpuOPRR.FcvtDS) ty x))
|
||||
|
||||
(rule
|
||||
(lower (has_type ty (fdemote x)))
|
||||
(fpu_rr (FpuOPRR.FcvtSD) ty x))
|
||||
|
||||
|
||||
;;;;; Rules for `for float arithmatic`
|
||||
(rule
|
||||
(lower (has_type ty (fadd x y)))
|
||||
(fpu_rrr (f_arithmatic_op ty (Opcode.Fadd)) ty x y))
|
||||
(rule
|
||||
(lower (has_type ty (fsub x y)))
|
||||
(fpu_rrr (f_arithmatic_op ty (Opcode.Fsub)) ty x y))
|
||||
(rule
|
||||
(lower (has_type ty (fmul x y)))
|
||||
(fpu_rrr (f_arithmatic_op ty (Opcode.Fmul)) ty x y))
|
||||
(rule
|
||||
(lower (has_type ty (fdiv x y)))
|
||||
(fpu_rrr (f_arithmatic_op ty (Opcode.Fdiv)) ty x y))
|
||||
|
||||
(rule
|
||||
(lower (has_type ty (fmin x y)))
|
||||
(gen_float_select (FloatSelectOP.Min) x y ty))
|
||||
|
||||
(rule
|
||||
(lower (has_type ty (fmin_pseudo x y)))
|
||||
(gen_float_select_pseudo (FloatSelectOP.Min) x y ty))
|
||||
|
||||
(rule
|
||||
(lower (has_type ty (fmax x y)))
|
||||
(gen_float_select (FloatSelectOP.Max) x y ty))
|
||||
|
||||
(rule
|
||||
(lower (has_type ty (fmax_pseudo x y)))
|
||||
(gen_float_select_pseudo (FloatSelectOP.Max) x y ty))
|
||||
|
||||
;;;;; Rules for `stack_addr`;;;;;;;;;
|
||||
(rule
|
||||
(lower (stack_addr ss offset))
|
||||
(gen_stack_addr ss offset))
|
||||
|
||||
;;;;; Rules for `is_null`;;;;;;;;;
|
||||
(rule
|
||||
(lower (is_null v))
|
||||
(gen_reference_check (ReferenceCheckOP.IsNull) v))
|
||||
|
||||
;;;;; Rules for `is_invalid`;;;;;;;;;
|
||||
(rule
|
||||
(lower (is_invalid v))
|
||||
(gen_reference_check (ReferenceCheckOP.IsInvalid) v))
|
||||
|
||||
;;;;; Rules for `select`;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type ty (select c x y)))
|
||||
(gen_select ty c x y)
|
||||
)
|
||||
|
||||
;;;;; Rules for `bitselect`;;;;;;;;;
|
||||
|
||||
(rule
|
||||
(lower (has_type ty (bitselect c x y)))
|
||||
(gen_bitselect ty c x y))
|
||||
|
||||
;;;;; Rules for `bint`;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type (fits_in_64 ty) (bint (valueregs_2_reg x))))
|
||||
(gen_bint x))
|
||||
(rule
|
||||
(lower (has_type $I128 (bint (valueregs_2_reg x))))
|
||||
(let ((tmp Reg (gen_bint x)))
|
||||
(value_regs tmp (zero_reg)))
|
||||
)
|
||||
|
||||
;;;;; Rules for `isplit`;;;;;;;;;
|
||||
(rule
|
||||
(lower (isplit x))
|
||||
(let
|
||||
((t1 Reg (gen_move2 (value_regs_get x 0) $I64 $I64))
|
||||
(t2 Reg (gen_move2 (value_regs_get x 1) $I64 $I64)))
|
||||
(output_pair t1 t2)))
|
||||
|
||||
;;;;; Rules for `iconcat`;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type $I128 (iconcat x y)))
|
||||
(let
|
||||
((t1 Reg (gen_move2 x $I64 $I64))
|
||||
(t2 Reg (gen_move2 y $I64 $I64)))
|
||||
(value_regs t1 t2)))
|
||||
|
||||
;;;;; Rules for `imax`;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type ty (imax x y)))
|
||||
(gen_int_select ty (IntSelectOP.Imax) (ext_int_if_need $true x ty) (ext_int_if_need $true y ty)))
|
||||
|
||||
;;;;; Rules for `imin`;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type ty (imin x y)))
|
||||
(gen_int_select ty(IntSelectOP.Imin) (ext_int_if_need $true x ty) (ext_int_if_need $true y ty)))
|
||||
;;;;; Rules for `umax`;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type ty (umax x y)))
|
||||
(gen_int_select ty(IntSelectOP.Umax) (ext_int_if_need $false x ty) (ext_int_if_need $false y ty)))
|
||||
|
||||
;;;;; Rules for `umin`;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type ty (umin x y)))
|
||||
(gen_int_select ty(IntSelectOP.Umin) (ext_int_if_need $false x ty) (ext_int_if_need $false y ty)))
|
||||
|
||||
;;;;; Rules for `debugtrap`;;;;;;;;;
|
||||
(rule
|
||||
(lower (debugtrap))
|
||||
(side_effect (SideEffectNoResult.Inst(MInst.EBreak))))
|
||||
|
||||
;;;;; Rules for `fence`;;;;;;;;;
|
||||
(rule
|
||||
(lower (fence))
|
||||
(side_effect (SideEffectNoResult.Inst(MInst.Fence 15 15))))
|
||||
|
||||
;;;;; Rules for `trap`;;;;;;;;;
|
||||
(rule
|
||||
(lower (trap code))
|
||||
(udf code))
|
||||
|
||||
;;;;; Rules for `resumable_trap`;;;;;;;;;
|
||||
(rule
|
||||
(lower (resumable_trap code))
|
||||
(udf code))
|
||||
|
||||
;;;;; Rules for `uload8`;;;;;;;;;
|
||||
(rule
|
||||
(lower (uload8 flags p offset))
|
||||
(gen_load p offset (int_load_op $false 8) flags $I64))
|
||||
;;;;; Rules for `sload8`;;;;;;;;;
|
||||
(rule
|
||||
(lower (sload8 flags p offset))
|
||||
(gen_load p offset (int_load_op $true 8) flags $I64))
|
||||
;;;;; Rules for `uload16`;;;;;;;;;
|
||||
(rule
|
||||
(lower (uload16 flags p offset))
|
||||
(gen_load p offset (int_load_op $false 16) flags $I64))
|
||||
|
||||
;;;;; Rules for `iload16`;;;;;;;;;
|
||||
(rule
|
||||
(lower (sload16 flags p offset))
|
||||
(gen_load p offset (int_load_op $true 16) flags $I64))
|
||||
|
||||
;;;;; Rules for `uload32`;;;;;;;;;
|
||||
(rule
|
||||
(lower (uload32 flags p offset))
|
||||
(gen_load p offset (int_load_op $false 32) flags $I64))
|
||||
|
||||
;;;;; Rules for `iload16`;;;;;;;;;
|
||||
(rule
|
||||
(lower (sload32 flags p offset))
|
||||
(gen_load p offset (int_load_op $true 32) flags $I64))
|
||||
|
||||
(rule
|
||||
(lower (has_type ty (load flags p offset)))
|
||||
(gen_load p offset (load_op ty) flags ty)
|
||||
)
|
||||
;;;; for I128
|
||||
(rule
|
||||
(lower (has_type $I128 (load flags p offset)))
|
||||
(gen_load_128 p offset flags))
|
||||
;;;; for B128
|
||||
(rule
|
||||
(lower (has_type $B128 (load flags p offset)))
|
||||
(gen_load_128 p offset flags))
|
||||
|
||||
;;;;; Rules for `istore8`;;;;;;;;;
|
||||
(rule
|
||||
(lower (istore8 flags x p offset))
|
||||
(gen_store p offset (StoreOP.Sb) flags x))
|
||||
;;;;; Rules for `istore16`;;;;;;;;;
|
||||
(rule
|
||||
(lower (istore16 flags x p offset))
|
||||
(gen_store p offset (StoreOP.Sh) flags x))
|
||||
|
||||
;;;;; Rules for `istore32`;;;;;;;;;
|
||||
(rule
|
||||
(lower (istore32 flags x p offset))
|
||||
(gen_store p offset (StoreOP.Sw) flags x))
|
||||
|
||||
;;;;; Rules for `store`;;;;;;;;;
|
||||
(rule
|
||||
(lower (store flags x @(value_type ty) p offset))
|
||||
(gen_store p offset (store_op ty) flags x))
|
||||
|
||||
;;; special for I128
|
||||
(rule
|
||||
(lower (store flags x @ (value_type $I128 ) p offset))
|
||||
(gen_store_128 p offset flags x))
|
||||
|
||||
;;; special for B128
|
||||
(rule
|
||||
(lower (store flags x @ (value_type $B128 ) p offset))
|
||||
(gen_store_128 p offset flags x))
|
||||
|
||||
(decl gen_icmp(IntCC ValueRegs ValueRegs Type)Reg)
|
||||
(rule
|
||||
(gen_icmp cc x y ty)
|
||||
(let
|
||||
((result WritableReg (temp_writable_reg $I64))
|
||||
(_ Unit (emit (MInst.Icmp cc result x y ty))))
|
||||
result))
|
||||
|
||||
;;;;; Rules for `icmp`;;;;;;;;;
|
||||
(rule
|
||||
(lower (icmp cc x @ (value_type ty) y))
|
||||
(lower_icmp cc x y ty))
|
||||
;; special for `iadd_ifcout` first out.
|
||||
(rule
|
||||
(lower (icmp cc (iadd_ifcout a @ (value_type ty) b) y))
|
||||
(lower_icmp cc (alu_add a b) y ty))
|
||||
|
||||
(rule
|
||||
(lower (icmp cc x (iadd_ifcout a @ (value_type ty) b)))
|
||||
(lower_icmp cc x (alu_add a b) ty))
|
||||
|
||||
(decl gen_fcmp(FloatCC Value Value Type)Reg)
|
||||
(rule
|
||||
(gen_fcmp cc x y ty)
|
||||
(let
|
||||
((result WritableReg (temp_writable_reg $I64))
|
||||
(_ Unit (emit (MInst.Fcmp cc result x y ty))))
|
||||
(writable_reg_to_reg result)))
|
||||
|
||||
;;;;; Rules for `fcmp`;;;;;;;;;
|
||||
(rule
|
||||
(lower (fcmp cc x @ (value_type ty) y))
|
||||
(gen_fcmp cc x y ty))
|
||||
|
||||
;;;;; Rules for `func_addr`;;;;;;;;;
|
||||
(rule
|
||||
(lower (func_addr (func_ref_data _ name _)))
|
||||
(load_ext_name name 0))
|
||||
|
||||
;;;;; Rules for `fcvt_to_uint`;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type to (fcvt_to_uint v @(value_type from))))
|
||||
(gen_fcvt_int $false v $false from to))
|
||||
|
||||
;;;;; Rules for `fcvt_to_sint`;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type to (fcvt_to_sint v @ (value_type from))))
|
||||
(gen_fcvt_int $false v $true from to))
|
||||
|
||||
;;;;; Rules for `fcvt_to_sint_sat`;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type to (fcvt_to_sint_sat v @ (value_type from))))
|
||||
(gen_fcvt_int $true v $true from to))
|
||||
|
||||
;;;;; Rules for `fcvt_to_uint_sat`;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type to (fcvt_to_uint_sat v @ (value_type from))))
|
||||
(gen_fcvt_int $true v $false from to))
|
||||
|
||||
;;;;; Rules for `fcvt_from_sint`;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type to (fcvt_from_sint v @ (value_type from))))
|
||||
(fpu_rr (int_convert_2_float_op from $true to) to v))
|
||||
|
||||
;;;;; Rules for `fcvt_from_uint`;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type to (fcvt_from_uint v @ (value_type from))))
|
||||
(fpu_rr (int_convert_2_float_op from $false to) to v))
|
||||
|
||||
;;;;; Rules for `symbol_value`;;;;;;;;;
|
||||
(rule
|
||||
(lower (symbol_value (symbol_value_data name _ offset)))
|
||||
(load_ext_name name offset)
|
||||
)
|
||||
;;;;; Rules for `bitcast`;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type out (bitcast v @ (value_type in_ty))))
|
||||
(gen_moves v in_ty out))
|
||||
|
||||
;;;;; Rules for `raw_bitcast`;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type out (raw_bitcast v @ (value_type in_ty))))
|
||||
(gen_moves v in_ty out))
|
||||
|
||||
;;;;; Rules for `ceil`;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type ty (ceil x)))
|
||||
(gen_float_round (FloatRoundOP.Ceil) x ty)
|
||||
)
|
||||
|
||||
;;;;; Rules for `floor`;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type ty (floor x)))
|
||||
(gen_float_round (FloatRoundOP.Floor) x ty))
|
||||
;;;;; Rules for `trunc`;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type ty (trunc x)))
|
||||
(gen_float_round (FloatRoundOP.Trunc) x ty))
|
||||
|
||||
;;;;; Rules for `nearest`;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type ty (nearest x)))
|
||||
(gen_float_round (FloatRoundOP.Nearest) x ty))
|
||||
|
||||
|
||||
;;;;; Rules for `selectif`;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type r_ty (selectif cc (ifcmp ca @ (value_type cty) cb) a b)))
|
||||
(let
|
||||
((dst VecWritableReg (alloc_vec_writable r_ty))
|
||||
(r Reg (lower_icmp cc ca cb cty))
|
||||
(_ Unit (emit (MInst.SelectIf $false (vec_writable_clone dst) r a b))))
|
||||
(vec_writable_to_regs dst)))
|
||||
|
||||
;;;;; Rules for `selectif_spectre_guard`;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type r_ty (selectif_spectre_guard cc (ifcmp ca @ (value_type cty) cb) a b)))
|
||||
(let
|
||||
((dst VecWritableReg (alloc_vec_writable r_ty))
|
||||
(r Reg (lower_icmp cc ca cb cty))
|
||||
(_ Unit (emit (MInst.SelectIf $true (vec_writable_clone dst) r a b))))
|
||||
(vec_writable_to_regs dst)))
|
||||
|
||||
;;;;; Rules for `trueif`;;;;;;;;;
|
||||
|
||||
(rule
|
||||
(lower (has_type ty (trueif cc (ifcmp ca @ (value_type cty) cb))))
|
||||
(lower_icmp cc ca cb cty))
|
||||
|
||||
;;;;; Rules for `trueff`;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type ty (trueff cc (ffcmp ca @ (value_type cty) cb))))
|
||||
(gen_fcmp cc ca cb cty))
|
||||
|
||||
|
||||
;;;;; Rules for `trapif`;;;;;;;;;
|
||||
(rule
|
||||
(lower (trapif cc (ifcmp a @ (value_type ty) b) trap_code))
|
||||
(let
|
||||
((test Reg (lower_icmp cc a b ty)))
|
||||
(gen_trapif test trap_code)))
|
||||
|
||||
(rule
|
||||
(lower (trapif _ (iadd_ifcout a @ (value_type ty) b) trap_code))
|
||||
(let
|
||||
((test Reg (lower_uadd_overflow a b ty)))
|
||||
(gen_trapif test trap_code)))
|
||||
|
||||
|
||||
;;;;; Rules for `trapff`;;;;;;;;;
|
||||
(rule
|
||||
(lower (trapff cc (ffcmp a @(value_type ty) b) trap_code))
|
||||
(gen_trapff cc a b ty trap_code))
|
||||
|
||||
;;;;; Rules for `bmask`;;;;;;;;;
|
||||
(rule
|
||||
;; because we encode bool all 1s.
|
||||
;; move is just ok.
|
||||
(lower (has_type (fits_in_64 ty) (bmask x @ (value_type ity))))
|
||||
(gen_move2 (value_regs_get x 0) ity ty))
|
||||
;;; for i128
|
||||
(rule
|
||||
;; because we encode bool all 1s.
|
||||
;; move is just ok.
|
||||
(lower (has_type $I128 (bmask x @ (value_type ity))))
|
||||
(value_regs (gen_move2 (value_regs_get x 0) $I64 $I64) (gen_move2 (value_regs_get x 0) $I64 $I64)))
|
||||
|
||||
;;;;; Rules for `bextend`;;;;;;;;;
|
||||
(rule
|
||||
;; because we encode bool all 1s.
|
||||
;; move is just ok.
|
||||
(lower (has_type ty (bextend x @ (value_type ity))))
|
||||
;;extra checks.
|
||||
(if-let _ (valid_bextend_ty ity ty))
|
||||
(gen_moves x ity ty))
|
||||
|
||||
;;; for B128
|
||||
(rule
|
||||
;; because we encode bool all 1s.
|
||||
;; move is just ok.
|
||||
(lower (has_type ty (bextend x @ (value_type ity))))
|
||||
;;extra checks.
|
||||
(if-let $B128 (valid_bextend_ty ity ty))
|
||||
(value_regs (gen_moves x $I64 $I64) (gen_moves x $I64 $I64)))
|
||||
|
||||
;; N.B.: the Ret itself is generated by the ABI.
|
||||
(rule (lower (return args))
|
||||
(lower_return (range 0 (value_slice_len args)) args))
|
||||
|
||||
|
||||
;;; Rules for `get_{frame,stack}_pointer` and `get_return_address` ;;;;;;;;;;;;;
|
||||
|
||||
(rule (lower (get_frame_pointer))
|
||||
(gen_move2 (x_reg 8) $I64 $I64))
|
||||
|
||||
(rule (lower (get_stack_pointer))
|
||||
(gen_move2 (x_reg 2) $I64 $I64))
|
||||
|
||||
(rule (lower (get_return_address))
|
||||
(load_ra))
|
||||
|
||||
;;; Rules for `iabs` ;;;;;;;;;;;;;
|
||||
(rule
|
||||
(lower (has_type (fits_in_64 ty) (iabs x)))
|
||||
(lower_iabs x ty))
|
||||
|
||||
;;;; Rules for calls ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
(rule (lower (call (func_ref_data sig_ref extname dist) inputs))
|
||||
(gen_call sig_ref extname dist inputs))
|
||||
|
||||
(rule (lower (call_indirect sig_ref val inputs))
|
||||
(gen_call_indirect sig_ref val inputs))
|
||||
Reference in New Issue
Block a user