add riscv64 backend for cranelift. (#4271)

Add a RISC-V 64 (`riscv64`, RV64GC) backend.

Co-authored-by: yuyang <756445638@qq.com>
Co-authored-by: Chris Fallin <chris@cfallin.org>
Co-authored-by: Afonso Bordado <afonsobordado@az8.co>

cranelift/codegen/meta/src/isa/mod.rs

@@ -4,6 +4,7 @@ use crate::shared::Definitions as SharedDefinitions;
 use std::fmt;
 
 mod arm64;
+mod riscv64;
 mod s390x;
 pub(crate) mod x86;
 
@@ -13,6 +14,7 @@ pub enum Isa {
     X86,
     Arm64,
     S390x,
+    Riscv64,
 }
 
 impl Isa {
@@ -30,13 +32,14 @@ impl Isa {
             "aarch64" => Some(Isa::Arm64),
             "s390x" => Some(Isa::S390x),
             x if ["x86_64", "i386", "i586", "i686"].contains(&x) => Some(Isa::X86),
+            "riscv64" | "riscv64gc" | "riscv64imac" => Some(Isa::Riscv64),
             _ => None,
         }
     }
 
     /// Returns all supported isa targets.
     pub fn all() -> &'static [Isa] {
-        &[Isa::X86, Isa::Arm64, Isa::S390x]
+        &[Isa::X86, Isa::Arm64, Isa::S390x, Isa::Riscv64]
     }
 }
 
@@ -47,6 +50,7 @@ impl fmt::Display for Isa {
             Isa::X86 => write!(f, "x86"),
             Isa::Arm64 => write!(f, "arm64"),
             Isa::S390x => write!(f, "s390x"),
+            Isa::Riscv64 => write!(f, "riscv64"),
         }
     }
 }
@@ -57,6 +61,7 @@ pub(crate) fn define(isas: &[Isa], shared_defs: &mut SharedDefinitions) -> Vec<T
             Isa::X86 => x86::define(shared_defs),
             Isa::Arm64 => arm64::define(shared_defs),
             Isa::S390x => s390x::define(shared_defs),
+            Isa::Riscv64 => riscv64::define(shared_defs),
         })
         .collect()
 }