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add riscv64 backend for cranelift. (#4271)

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Add a RISC-V 64 (`riscv64`, RV64GC) backend.

Co-authored-by: yuyang <756445638@qq.com>
Co-authored-by: Chris Fallin <chris@cfallin.org>
Co-authored-by: Afonso Bordado <afonsobordado@az8.co>
This commit is contained in:
yuyang-ok
2022-09-28 08:30:31 +08:00
committed by GitHub
parent 9715d91c50
commit cdecc858b4
182 changed files with 21024 additions and 36 deletions
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12
cranelift/codegen/build.rs
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@@ -187,6 +187,8 @@ fn get_isle_compilations(
let src_isa_s390x =
make_isle_source_path_relative(&cur_dir, crate_dir.join("src").join("isa").join("s390x"));
let src_isa_risc_v =
make_isle_source_path_relative(&cur_dir, crate_dir.join("src").join("isa").join("riscv64"));
// This is a set of ISLE compilation units.
//
// The format of each entry is:
@@ -234,6 +236,16 @@ fn get_isle_compilations(
],
untracked_inputs: vec![clif_isle.clone()],
},
// The risc-v instruction selector.
IsleCompilation {
output: out_dir.join("isle_riscv64.rs"),
inputs: vec![
prelude_isle.clone(),
src_isa_risc_v.join("inst.isle"),
src_isa_risc_v.join("lower.isle"),
],
untracked_inputs: vec![clif_isle.clone()],
},
],
})
}