Merge pull request #2682 from cfallin/shift-bugs

Fix some `i128` shift-related bugs in x64 backend.
2021-02-26 15:13:08 -08:00
parent 7795a230f2 6dcb31abb7
commit cdb60ec5a9
5 changed files with 144 additions and 316 deletions
--- a/cranelift/codegen/src/isa/x64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/x64/inst/emit.rs
@@ -1371,7 +1371,7 @@ pub(crate) fn emit(
                RegMemImm::Imm { simm32 } => {
                    // FIXME JRS 2020Feb11: there are shorter encodings for
                    // cmp $imm, rax/eax/ax/al.
-                    let use_imm8 = low8_will_sign_extend_to_32(*simm32);
+                    let use_imm8 = is_cmp && low8_will_sign_extend_to_32(*simm32);

                    // And also here we use the "normal" G-E ordering.
                    let opcode = if is_cmp {