Merge pull request #2682 from cfallin/shift-bugs

Fix some `i128` shift-related bugs in x64 backend.

cranelift/codegen/src/isa/x64/inst/emit.rs

@@ -1371,7 +1371,7 @@ pub(crate) fn emit(
                 RegMemImm::Imm { simm32 } => {
                     // FIXME JRS 2020Feb11: there are shorter encodings for
                     // cmp $imm, rax/eax/ax/al.
-                    let use_imm8 = low8_will_sign_extend_to_32(*simm32);
+                    let use_imm8 = is_cmp && low8_will_sign_extend_to_32(*simm32);
 
                     // And also here we use the "normal" G-E ordering.
                     let opcode = if is_cmp {

cranelift/codegen/src/isa/x64/inst/emit_tests.rs

@@ -2999,6 +2999,11 @@ fn test_x64_emit() {
         "48855763",
         "testq   99(%rdi), %rdx",
     ));
+    insns.push((
+        Inst::test_rmi_r(OperandSize::Size64, RegMemImm::imm(127), rdx),
+        "48F7C27F000000",
+        "testq   $127, %rdx",
+    ));
     insns.push((
         Inst::test_rmi_r(OperandSize::Size64, RegMemImm::imm(76543210), rdx),
         "48F7C2EAF48F04",