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Add encodings for Intel dynamic shift instructions.

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These instructions have a fixed register constraint; the shift amount is
passed in CL.

Add meta language syntax so a fixed register can be specified as
"GPR.rcx".
This commit is contained in:
Jakob Stoklund Olesen
2017-05-08 20:56:08 -07:00
parent db9f64d2f3
commit cdb3a71dd1
5 changed files with 72 additions and 5 deletions
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21
lib/cretonne/src/isa/intel/binemit.rs
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@@ -13,6 +13,7 @@ fn put_op1<CS: CodeSink + ?Sized>(bits: u16, sink: &mut CS) {
sink.put1(bits as u8);
}
/// Emit a ModR/M byte for reg-reg operands.
fn modrm_rr<CS: CodeSink + ?Sized>(rm: RegUnit, reg: RegUnit, sink: &mut CS) {
let reg = reg as u8 & 7;
let rm = rm as u8 & 7;
@@ -22,6 +23,16 @@ fn modrm_rr<CS: CodeSink + ?Sized>(rm: RegUnit, reg: RegUnit, sink: &mut CS) {
sink.put1(b);
}
/// Emit a ModR/M byte where the reg bits are part of the opcode.
fn modrm_r_bits<CS: CodeSink + ?Sized>(rm: RegUnit, bits: u16, sink: &mut CS) {
let reg = (bits >> 12) as u8 & 7;
let rm = rm as u8 & 7;
let mut b = 0b11000000;
b |= reg << 3;
b |= rm;
sink.put1(b);
}
fn recipe_op1rr<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
if let InstructionData::Binary { args, .. } = func.dfg[inst] {
put_op1(func.encodings[inst].bits(), sink);
@@ -32,3 +43,13 @@ fn recipe_op1rr<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut C
panic!("Expected Binary format: {:?}", func.dfg[inst]);
}
}
fn recipe_op1rc<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
if let InstructionData::Binary { args, .. } = func.dfg[inst] {
let bits = func.encodings[inst].bits();
put_op1(bits, sink);
modrm_r_bits(func.locations[args[0]].unwrap_reg(), bits, sink);
} else {
panic!("Expected Binary format: {:?}", func.dfg[inst]);
}
}