T0b1/wasmtime
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add encodings for Intel dynamic shift instructions.

Browse Source 
These instructions have a fixed register constraint; the shift amount is
passed in CL.

Add meta language syntax so a fixed register can be specified as
"GPR.rcx".
This commit is contained in:
Jakob Stoklund Olesen
2017-05-08 20:56:08 -07:00
parent db9f64d2f3
commit cdb3a71dd1
5 changed files with 72 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
lib/cretonne/meta/isa/intel/encodings.py
View File

@@ -4,7 +4,14 @@ Intel Encodings.
from __future__ import absolute_import
from base import instructions as base
from .defs import I32
from .recipes import Op1rr
from .recipes import Op1rr, Op1rc
from .recipes import OP
I32.enc(base.iadd.i32, Op1rr, OP(0x01))
# 32-bit shifts and rotates.
# Note that the dynamic shift amount is only masked by 5 or 6 bits; the 8-bit
# and 16-bit shifts would need explicit masking.
I32.enc(base.ishl.i32.i32, Op1rc, OP(0xd3, rrr=4))
I32.enc(base.ushr.i32.i32, Op1rc, OP(0xd3, rrr=5))
I32.enc(base.sshr.i32.i32, Op1rc, OP(0xd3, rrr=7))