x64: Misc small integer fixes
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@@ -50,6 +50,15 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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match op {
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Opcode::Iconst | Opcode::Bconst | Opcode::Null => {
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let value = ctx.get_constant(insn).unwrap();
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// Sign extend constant if necessary
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let value = match ty.unwrap() {
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I8 => (((value as i64) << 8) >> 8) as u64,
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I16 => (((value as i64) << 16) >> 16) as u64,
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I32 => (((value as i64) << 32) >> 32) as u64,
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I64 | R64 => value,
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ty if ty.is_bool() => value,
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ty => unreachable!("Unknown type for const: {}", ty),
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};
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let rd = get_output_reg(ctx, outputs[0]);
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lower_constant_u64(ctx, rd, value);
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}
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@@ -179,12 +179,13 @@ fn extend_input_to_reg(ctx: Ctx, spec: InsnInput, ext_spec: ExtSpec) -> Reg {
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let ext_mode = match (input_size, requested_size) {
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(a, b) if a == b => return input_to_reg(ctx, spec),
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(a, 32) if a == 1 || a == 8 => ExtMode::BL,
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(1, 8) => return input_to_reg(ctx, spec),
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(a, 16) | (a, 32) if a == 1 || a == 8 => ExtMode::BL,
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(a, 64) if a == 1 || a == 8 => ExtMode::BQ,
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(16, 32) => ExtMode::WL,
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(16, 64) => ExtMode::WQ,
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(32, 64) => ExtMode::LQ,
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_ => unreachable!(),
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_ => unreachable!("extend {} -> {}", input_size, requested_size),
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};
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let src = input_to_reg_mem(ctx, spec);
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@@ -1108,7 +1109,7 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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let dst = output_to_reg(ctx, outputs[0]);
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let ext_mode = match (src_ty.bits(), dst_ty.bits()) {
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(1, 32) | (8, 32) => Some(ExtMode::BL),
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(1, 8) | (1, 16) | (1, 32) | (8, 16) | (8, 32) => Some(ExtMode::BL),
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(1, 64) | (8, 64) => Some(ExtMode::BQ),
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(16, 32) => Some(ExtMode::WL),
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(16, 64) => Some(ExtMode::WQ),
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