diff --git a/cranelift/codegen/meta/src/isa/x86/mod.rs b/cranelift/codegen/meta/src/isa/x86/mod.rs
index bf59b8d9c1..dba5737062 100644
--- a/cranelift/codegen/meta/src/isa/x86/mod.rs
+++ b/cranelift/codegen/meta/src/isa/x86/mod.rs
@@ -1,6 +1,5 @@
 use crate::cdsl::cpu_modes::CpuMode;
 use crate::cdsl::isa::TargetIsa;
-use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder};
 
 use crate::shared::types::Bool::B1;
 use crate::shared::types::Float::{F32, F64};
@@ -9,52 +8,12 @@ use crate::shared::Definitions as SharedDefinitions;
 
 mod instructions;
 mod legalize;
+mod registers;
 mod settings;
 
-fn define_registers() -> IsaRegs {
-    let mut regs = IsaRegsBuilder::new();
-
-    let builder = RegBankBuilder::new("IntRegs", "r")
-        .units(16)
-        .names(vec!["rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi"])
-        .track_pressure(true);
-    let int_regs = regs.add_bank(builder);
-
-    let builder = RegBankBuilder::new("FloatRegs", "xmm")
-        .units(16)
-        .track_pressure(true);
-    let float_regs = regs.add_bank(builder);
-
-    let builder = RegBankBuilder::new("FlagRegs", "")
-        .units(1)
-        .names(vec!["rflags"])
-        .track_pressure(false);
-    let flag_reg = regs.add_bank(builder);
-
-    let builder = RegClassBuilder::new_toplevel("GPR", int_regs);
-    let gpr = regs.add_class(builder);
-
-    let builder = RegClassBuilder::new_toplevel("FPR", float_regs);
-    let fpr = regs.add_class(builder);
-
-    let builder = RegClassBuilder::new_toplevel("FLAG", flag_reg);
-    regs.add_class(builder);
-
-    let builder = RegClassBuilder::subclass_of("GPR8", gpr, 0, 8);
-    let gpr8 = regs.add_class(builder);
-
-    let builder = RegClassBuilder::subclass_of("ABCD", gpr8, 0, 4);
-    regs.add_class(builder);
-
-    let builder = RegClassBuilder::subclass_of("FPR8", fpr, 0, 8);
-    regs.add_class(builder);
-
-    regs.finish()
-}
-
 pub fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
     let settings = settings::define(&shared_defs.settings);
-    let regs = define_registers();
+    let regs = registers::define();
 
     let inst_group = instructions::define(&shared_defs.format_registry);
     legalize::define(shared_defs, &inst_group);
diff --git a/cranelift/codegen/meta/src/isa/x86/registers.rs b/cranelift/codegen/meta/src/isa/x86/registers.rs
new file mode 100644
index 0000000000..350a5d904e
--- /dev/null
+++ b/cranelift/codegen/meta/src/isa/x86/registers.rs
@@ -0,0 +1,42 @@
+use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder};
+
+pub fn define() -> IsaRegs {
+    let mut regs = IsaRegsBuilder::new();
+
+    let builder = RegBankBuilder::new("IntRegs", "r")
+        .units(16)
+        .names(vec!["rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi"])
+        .track_pressure(true);
+    let int_regs = regs.add_bank(builder);
+
+    let builder = RegBankBuilder::new("FloatRegs", "xmm")
+        .units(16)
+        .track_pressure(true);
+    let float_regs = regs.add_bank(builder);
+
+    let builder = RegBankBuilder::new("FlagRegs", "")
+        .units(1)
+        .names(vec!["rflags"])
+        .track_pressure(false);
+    let flag_reg = regs.add_bank(builder);
+
+    let builder = RegClassBuilder::new_toplevel("GPR", int_regs);
+    let gpr = regs.add_class(builder);
+
+    let builder = RegClassBuilder::new_toplevel("FPR", float_regs);
+    let fpr = regs.add_class(builder);
+
+    let builder = RegClassBuilder::new_toplevel("FLAG", flag_reg);
+    regs.add_class(builder);
+
+    let builder = RegClassBuilder::subclass_of("GPR8", gpr, 0, 8);
+    let gpr8 = regs.add_class(builder);
+
+    let builder = RegClassBuilder::subclass_of("ABCD", gpr8, 0, 4);
+    regs.add_class(builder);
+
+    let builder = RegClassBuilder::subclass_of("FPR8", fpr, 0, 8);
+    regs.add_class(builder);
+
+    regs.finish()
+}