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machinst x64: inline helper used only once;

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This commit is contained in:
Benjamin Bouvier
2020-09-08 16:10:23 +02:00
parent 7a833f442a
commit cb96d16ac7
1 changed files with 6 additions and 11 deletions
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17
cranelift/codegen/src/isa/x64/lower.rs
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@@ -53,10 +53,6 @@ fn is_valid_atomic_transaction_ty(ty: Type) -> bool {
} }
} }
fn iri_to_u64_imm(ctx: Ctx, inst: IRInst) -> Option<u64> {
ctx.get_constant(inst)
}
/// Returns whether the given specified `input` is a result produced by an instruction with Opcode /// Returns whether the given specified `input` is a result produced by an instruction with Opcode
/// `op`. /// `op`.
// TODO investigate failures with checking against the result index. // TODO investigate failures with checking against the result index.
@@ -454,13 +450,12 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
match op { match op {
Opcode::Iconst | Opcode::Bconst | Opcode::Null => { Opcode::Iconst | Opcode::Bconst | Opcode::Null => {
if let Some(w64) = iri_to_u64_imm(ctx, insn) { let w64 = ctx
let dst_is_64 = w64 > 0x7fffffff; .get_constant(insn)
let dst = get_output_reg(ctx, outputs[0]); .expect("constant value for iconst et al");
ctx.emit(Inst::imm_r(dst_is_64, w64, dst)); let dst_is_64 = w64 > 0x7fffffff;
} else { let dst = get_output_reg(ctx, outputs[0]);
unimplemented!(); ctx.emit(Inst::imm_r(dst_is_64, w64, dst));
}
} }
Opcode::Iadd Opcode::Iadd