Switch default to new x86_64 backend.
This PR switches the default backend on x86, for both the `cranelift-codegen` crate and for Wasmtime, to the new (`MachInst`-style, `VCode`-based) backend that has been under development and testing for some time now. The old backend is still available by default in builds with the `old-x86-backend` feature, or by requesting `BackendVariant::Legacy` from the appropriate APIs. As part of that switch, it adds some more runtime-configurable plumbing to the testing infrastructure so that tests can be run using the appropriate backend. `clif-util test` is now capable of parsing a backend selector option from filetests and instantiating the correct backend. CI has been updated so that the old x86 backend continues to run its tests, just as we used to run the new x64 backend separately. At some point, we will remove the old x86 backend entirely, once we are satisfied that the new backend has not caused any unforeseen issues and we do not need to revert.
This commit is contained in:
Chris Fallin
@@ -1,5 +1,5 @@
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test regalloc
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target x86_64 haswell
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target x86_64 legacy haswell
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function %value_aliases(i32, f32, i64 vmctx) baldrdash_system_v {
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gv0 = vmctx
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@@ -1,5 +1,5 @@
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test regalloc
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target x86_64 haswell
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target x86_64 legacy haswell
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; Reported as https://github.com/bytecodealliance/cranelift/issues/207
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;
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@@ -1,5 +1,5 @@
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test regalloc
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target x86_64 haswell
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target x86_64 legacy haswell
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; Reported as https://github.com/bytecodealliance/cranelift/issues/216 from the Binaryen fuzzer.
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;
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@@ -1,5 +1,5 @@
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test regalloc
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target x86_64 haswell
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target x86_64 legacy haswell
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function %pr227(i32 [%rdi], i32 [%rsi], i32 [%rdx], i32 [%rcx], i64 vmctx [%r8]) system_v {
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gv0 = vmctx
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@@ -1,5 +1,5 @@
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test regalloc
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target x86_64
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target x86_64 legacy
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; Test that fallthrough returns are visited by reload and coloring.
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@@ -1,5 +1,5 @@
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test regalloc
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target x86_64 haswell
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target x86_64 legacy haswell
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; This test case would create a block parameter that was a ghost value.
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; The coalescer would insert a copy of the ghost value, leading to verifier errors.
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@@ -1,5 +1,5 @@
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test regalloc
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target i686
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target i686 legacy
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; This test covers the troubles when values with global live ranges are defined
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; by instructions with constrained register classes.
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@@ -1,5 +1,5 @@
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test regalloc
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target x86_64 haswell
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target x86_64 legacy haswell
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function %foo() system_v {
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block4:
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@@ -1,5 +1,5 @@
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test regalloc
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target x86_64
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target x86_64 legacy
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function u0:587() fast {
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block0:
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@@ -1,5 +1,5 @@
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test regalloc
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target x86_64 haswell
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target x86_64 legacy haswell
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function u0:9(i64 [%rdi], f32 [%xmm0], f64 [%xmm1], i32 [%rsi], i32 [%rdx], i64 vmctx [%r14]) -> i64 [%rax] baldrdash_system_v {
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block0(v0: i64, v1: f32, v2: f64, v3: i32, v4: i32, v5: i64):
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@@ -1,5 +1,5 @@
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test regalloc
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target x86_64 haswell
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target x86_64 legacy haswell
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; Test combinations of constraints.
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;
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@@ -1,5 +1,5 @@
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test regalloc
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target x86_64
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target x86_64 legacy
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; Return the same value twice. This needs a copy so that each value can be
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; allocated its own register.
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@@ -1,5 +1,5 @@
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test regalloc
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target x86_64 haswell
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target x86_64 legacy haswell
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function %test(i64) -> i64 system_v {
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block0(v0: i64):
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@@ -1,5 +1,5 @@
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test regalloc
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target x86_64 haswell
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target x86_64 legacy haswell
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; regex: V=v\d+
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; regex: BB=block\d+
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@@ -1,5 +1,5 @@
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test compile
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target x86_64
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target x86_64 legacy
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; Filed as https://github.com/bytecodealliance/cranelift/issues/779
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;
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@@ -1,5 +1,5 @@
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test regalloc
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target riscv32 enable_e
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target riscv32 legacy enable_e
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; regex: V=v\d+
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@@ -1,5 +1,5 @@
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test regalloc
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target i686 haswell
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target i686 legacy haswell
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function %pr165() system_v {
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block0:
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@@ -1,7 +1,7 @@
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test compile
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set opt_level=speed
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set enable_pinned_reg=true
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target x86_64 haswell
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target x86_64 legacy haswell
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function u0:0(i32, i32, i32, i64 vmctx) -> i64 uext system_v {
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block0(v0: i32, v1: i32, v2: i32, v3: i64):
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@@ -1,7 +1,7 @@
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test compile
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set opt_level=speed
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set enable_pinned_reg=true
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target x86_64 haswell
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target x86_64 legacy haswell
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function u0:0(i32, i32, i32, i64 vmctx) -> i64 uext system_v {
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block0(v0: i32, v1: i32, v2: i32, v3: i64):
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@@ -1,7 +1,7 @@
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test compile
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set opt_level=speed
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set enable_pinned_reg=true
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target x86_64 haswell
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target x86_64 legacy haswell
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;; Test for the issue #1123; https://github.com/bytecodealliance/cranelift/issues/1123
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@@ -1,5 +1,5 @@
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test regalloc
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target x86_64
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target x86_64 legacy
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; Test case found by the Binaryen fuzzer.
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;
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@@ -12,7 +12,7 @@ test regalloc
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; regex: V=v\d+
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; regex: WS=\s+
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target riscv32 enable_e
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target riscv32 legacy enable_e
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; In straight-line code, the first value defined is spilled.
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; That is in order:
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@@ -2,7 +2,7 @@
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test compile
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set enable_probestack=0
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target x86_64 haswell
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target x86_64 legacy haswell
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; This function contains unreachable blocks which trip up the register
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; allocator if they don't get cleared out.
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@@ -1,5 +1,5 @@
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test regalloc
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target i686
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target i686 legacy
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; regex: V=v\d+
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; regex: BB=block\d+
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