Switch default to new x86_64 backend.

This PR switches the default backend on x86, for both the
`cranelift-codegen` crate and for Wasmtime, to the new
(`MachInst`-style, `VCode`-based) backend that has been under
development and testing for some time now.

The old backend is still available by default in builds with the
`old-x86-backend` feature, or by requesting `BackendVariant::Legacy`
from the appropriate APIs.

As part of that switch, it adds some more runtime-configurable plumbing
to the testing infrastructure so that tests can be run using the
appropriate backend. `clif-util test` is now capable of parsing a
backend selector option from filetests and instantiating the correct
backend.

CI has been updated so that the old x86 backend continues to run its
tests, just as we used to run the new x64 backend separately.

At some point, we will remove the old x86 backend entirely, once we are
satisfied that the new backend has not caused any unforeseen issues and
we do not need to revert.

cranelift/Cargo.toml

@@ -50,7 +50,6 @@ default = ["disas", "wasm", "cranelift-codegen/all-arch", "peepmatic-souper", "s
 disas = ["capstone"]
 enable-peepmatic = ["cranelift-codegen/enable-peepmatic", "cranelift-filetests/enable-peepmatic"]
 wasm = ["wat", "cranelift-wasm"]
-experimental_x64 = ["cranelift-codegen/x64", "cranelift-filetests/experimental_x64", "cranelift-reader/experimental_x64"]
 experimental_arm32 = ["cranelift-codegen/arm32", "cranelift-filetests/experimental_arm32"]
 souper-harvest = ["cranelift-codegen/souper-harvest", "rayon"]
 all-arch = ["cranelift-codegen/all-arch"]

cranelift/codegen/Cargo.toml

@@ -63,9 +63,15 @@ unwind = ["gimli"]
 x86 = []
 arm64 = []
 riscv = []
-x64 = [] # New work-in-progress codegen backend for x86_64 based on the new isel.
 arm32 = [] # Work-in-progress codegen backend for ARM.
 
+# Stub feature that does nothing, for Cargo-features compatibility: the new
+# backend is the default now.
+experimental_x64 = []
+
+# Make the old x86 backend the default.
+old-x86-backend = []
+
 # Option to enable all architectures.
 all-arch = [
     "x86",

cranelift/codegen/src/isa/mod.rs

@@ -74,16 +74,15 @@ use thiserror::Error;
 #[cfg(feature = "riscv")]
 mod riscv;
 
-// N.B.: the old x86-64 backend (`x86`) and the new one (`x64`) can both be
-// included; if the new backend is included, then it is the default backend
-// returned for an x86-64 triple, but a specific option can request the old
-// backend. It is important to have the ability to instantiate *both* backends
-// in the same build so that we can do things like differential fuzzing between
-// backends, or perhaps offer a runtime configuration flag in the future.
+// N.B.: the old x86-64 backend (`x86`) and the new one (`x64`) are both
+// included whenever building with x86 support. The new backend is the default,
+// but the old can be requested with `BackendVariant::Legacy`. However, if this
+// crate is built with the `old-x86-backend` feature, then the old backend is
+// default instead.
 #[cfg(feature = "x86")]
 mod x86;
 
-#[cfg(feature = "x64")]
+#[cfg(feature = "x86")]
 mod x64;
 
 #[cfg(feature = "arm32")]
@@ -122,7 +121,7 @@ macro_rules! isa_builder {
 /// The "variant" for a given target. On one platform (x86-64), we have two
 /// backends, the "old" and "new" one; the new one is the default if included
 /// in the build configuration and not otherwise specified.
-#[derive(Clone, Copy)]
+#[derive(Clone, Copy, Debug)]
 pub enum BackendVariant {
     /// Any backend available.
     Any,
@@ -149,13 +148,13 @@ pub fn lookup_variant(triple: Triple, variant: BackendVariant) -> Result<Builder
             isa_builder!(x86, (feature = "x86"), triple)
         }
         (Architecture::X86_64, BackendVariant::MachInst) => {
-            isa_builder!(x64, (feature = "x64"), triple)
+            isa_builder!(x64, (feature = "x86"), triple)
         }
-        #[cfg(feature = "x64")]
+        #[cfg(not(feature = "old-x86-backend"))]
         (Architecture::X86_64, BackendVariant::Any) => {
-            isa_builder!(x64, (feature = "x64"), triple)
+            isa_builder!(x64, (feature = "x86"), triple)
         }
-        #[cfg(not(feature = "x64"))]
+        #[cfg(feature = "old-x86-backend")]
         (Architecture::X86_64, BackendVariant::Any) => {
             isa_builder!(x86, (feature = "x86"), triple)
         }
@@ -277,7 +276,13 @@ pub trait TargetIsa: fmt::Display + Send + Sync {
     /// Get the ISA-dependent flag values that were used to make this trait object.
     fn isa_flags(&self) -> Vec<settings::Value>;
 
-    /// Hashes all flags, both ISA-independent and ISA-dependent, into the specified hasher.
+    /// Get the variant of this ISA (Legacy or MachInst).
+    fn variant(&self) -> BackendVariant {
+        BackendVariant::Legacy
+    }
+
+    /// Hashes all flags, both ISA-independent and ISA-specific, into the
+    /// specified hasher.
     fn hash_all_flags(&self, hasher: &mut dyn Hasher);
 
     /// Get the default calling convention of this target.

cranelift/codegen/src/isa/unwind/winx64.rs

@@ -8,9 +8,7 @@ use log::warn;
 #[cfg(feature = "enable-serde")]
 use serde::{Deserialize, Serialize};
 
-#[cfg(feature = "x64")]
 use crate::binemit::CodeOffset;
-#[cfg(feature = "x64")]
 use crate::isa::unwind::UnwindInst;
 
 /// Maximum (inclusive) size of a "small" stack allocation
@@ -334,10 +332,8 @@ impl UnwindInfo {
     }
 }
 
-#[cfg(feature = "x64")]
 const UNWIND_RBP_REG: u8 = 5;
 
-#[cfg(feature = "x64")]
 pub(crate) fn create_unwind_info_from_insts<MR: RegisterMapper<regalloc::Reg>>(
     insts: &[(CodeOffset, UnwindInst)],
 ) -> CodegenResult<UnwindInfo> {

cranelift/codegen/src/isa/x64/inst/unwind/systemv.rs

@@ -109,6 +109,7 @@ mod tests {
     use target_lexicon::triple;
 
     #[test]
+    #[cfg_attr(feature = "old-x86-backend", ignore)]
     fn test_simple_func() {
         let isa = lookup(triple!("x86_64"))
             .expect("expect x86 ISA")
@@ -151,6 +152,7 @@ mod tests {
     }
 
     #[test]
+    #[cfg_attr(feature = "old-x86-backend", ignore)]
     fn test_multi_return_func() {
         let isa = lookup(triple!("x86_64"))
             .expect("expect x86 ISA")

cranelift/codegen/src/machinst/adapter.rs

@@ -2,7 +2,9 @@
 
 use crate::binemit;
 use crate::ir;
-use crate::isa::{EncInfo, Encoding, Encodings, Legalize, RegClass, RegInfo, TargetIsa};
+use crate::isa::{
+    BackendVariant, EncInfo, Encoding, Encodings, Legalize, RegClass, RegInfo, TargetIsa,
+};
 use crate::machinst::*;
 use crate::regalloc::RegisterSet;
 use crate::settings::{self, Flags};
@@ -62,6 +64,10 @@ impl TargetIsa for TargetIsaAdapter {
         self.backend.isa_flags()
     }
 
+    fn variant(&self) -> BackendVariant {
+        BackendVariant::MachInst
+    }
+
     fn hash_all_flags(&self, hasher: &mut dyn Hasher) {
         self.backend.hash_all_flags(hasher);
     }

cranelift/filetests/Cargo.toml

@@ -30,4 +30,3 @@ anyhow = "1.0.32"
 [features]
 enable-peepmatic = []
 experimental_arm32 = []
-experimental_x64 = []

cranelift/filetests/filetests/isa/x64/amode-opt.clif

@@ -1,6 +1,5 @@
 test compile
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %amode_add(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):

cranelift/filetests/filetests/isa/x64/b1.clif

@@ -1,6 +1,5 @@
 test compile
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %f0(b1, i32, i32) -> i32 {
 ; check:  pushq   %rbp

cranelift/filetests/filetests/isa/x64/basic.clif

@@ -1,6 +1,5 @@
 test compile
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %f(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):

cranelift/filetests/filetests/isa/x64/bitops-i128-run.clif

@@ -1,6 +1,5 @@
 test run
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %ctz(i64, i64) -> i8 {
 block0(v0: i64, v1: i64):

cranelift/filetests/filetests/isa/x64/bitrev-i128-run.clif

@@ -1,6 +1,5 @@
 test run
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %reverse_bits_zero() -> b1 {
 block0:

cranelift/filetests/filetests/isa/x64/branches.clif

@@ -1,6 +1,5 @@
 test compile
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %f0(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):

cranelift/filetests/filetests/isa/x64/clz-lzcnt.clif

@@ -1,6 +1,5 @@
 test compile
-target x86_64 has_lzcnt
-feature "experimental_x64"
+target x86_64 machinst has_lzcnt
 
 function %clz(i64) -> i64 {
 block0(v0: i64):

cranelift/filetests/filetests/isa/x64/cmp-mem-bug.clif

@@ -1,6 +1,5 @@
 test compile
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %f0(i64, i64) -> i64, i64 {
 block0(v0: i64, v1: i64):

cranelift/filetests/filetests/isa/x64/ctz-bmi1.clif

@@ -1,6 +1,5 @@
 test compile
-target x86_64 has_bmi1
-feature "experimental_x64"
+target x86_64 machinst has_bmi1
 
 function %ctz(i64) -> i64 {
 block0(v0: i64):

cranelift/filetests/filetests/isa/x64/div-checks-run.clif

@@ -1,7 +1,6 @@
 test run
 set avoid_div_traps=false
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %f0(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):

cranelift/filetests/filetests/isa/x64/div-checks.clif

@@ -1,7 +1,6 @@
 test compile
 set avoid_div_traps=false
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 ;; We should get the checked-div/rem sequence (`srem` pseudoinst below) even
 ;; when `avoid_div_traps` above is false (i.e. even when the host is normally

cranelift/filetests/filetests/isa/x64/fastcall.clif

@@ -1,8 +1,7 @@
 test compile
 set enable_llvm_abi_extensions=true
 set unwind_info=true
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %f0(i64, i64, i64, i64) -> i64 windows_fastcall {
 block0(v0: i64, v1: i64, v2: i64, v3: i64):

cranelift/filetests/filetests/isa/x64/floating-point.clif

@@ -1,6 +1,5 @@
 test compile
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %f(f64) -> f64 {
 block0(v0: f64):

cranelift/filetests/filetests/isa/x64/heap.clif

@@ -1,6 +1,5 @@
 test compile
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %f(i32, i64 vmctx) -> i64 {
     gv0 = vmctx

cranelift/filetests/filetests/isa/x64/i128.clif

@@ -1,7 +1,6 @@
 test compile
 set enable_llvm_abi_extensions=true
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %f0(i128, i128) -> i128 {
 ; check:   pushq   %rbp

cranelift/filetests/filetests/isa/x64/icmp-i128-run.clif

@@ -1,6 +1,5 @@
 test run
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %test_icmp_eq_i128() -> b1 {
 block0:

cranelift/filetests/filetests/isa/x64/load-op.clif

@@ -1,6 +1,5 @@
 test compile
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %add_from_mem_u32_1(i64, i32) -> i32 {
 block0(v0: i64, v1: i32):

cranelift/filetests/filetests/isa/x64/move-elision.clif

@@ -1,7 +1,6 @@
 test compile
 set enable_simd
-target x86_64 skylake
-feature "experimental_x64"
+target x86_64 machinst skylake
 
 function %move_registers(i32x4) -> b8x16 {
 block0(v0: i32x4):

cranelift/filetests/filetests/isa/x64/popcnt-use-popcnt.clif

@@ -1,6 +1,5 @@
 test compile
-target x86_64 has_popcnt has_sse42
-feature "experimental_x64"
+target x86_64 machinst has_popcnt has_sse42
 
 function %popcnt(i64) -> i64 {
 block0(v0: i64):

cranelift/filetests/filetests/isa/x64/popcnt.clif

@@ -1,6 +1,5 @@
 test compile
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %popcnt64(i64) -> i64 {
 block0(v0: i64):

cranelift/filetests/filetests/isa/x64/probestack.clif

@@ -1,7 +1,6 @@
 test compile
 set enable_probestack=true
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %f1() -> i64 {
 ss0 = explicit_slot 100000

cranelift/filetests/filetests/isa/x64/run-const.clif

@@ -1,6 +1,5 @@
 test run
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %test_compare_i32() -> b1 {
 block0:

cranelift/filetests/filetests/isa/x64/select-i128.clif

@@ -1,7 +1,6 @@
 test compile
 set enable_llvm_abi_extensions=true
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %f0(i32, i128, i128) -> i128 {
 ; check:   pushq   %rbp

cranelift/filetests/filetests/isa/x64/shift-i128-run.clif

@@ -1,6 +1,5 @@
 test run
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %ishl(i64, i64, i8) -> i64, i64 {
 block0(v0: i64, v1: i64, v2: i8):

cranelift/filetests/filetests/isa/x64/simd-arithmetic-run.clif

@@ -1,7 +1,6 @@
 test run
 set enable_simd
-target x86_64 skylake
-feature "experimental_x64"
+target x86_64 machinst skylake
 
 function %iadd_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0:i32x4, v1:i32x4):

cranelift/filetests/filetests/isa/x64/simd-bitwise-compile.clif

@@ -1,7 +1,6 @@
 test compile
 set enable_simd
-target x86_64 skylake
-feature "experimental_x64"
+target x86_64 machinst skylake
 
 function %bitselect_i16x8() -> i16x8 {
 block0:

cranelift/filetests/filetests/isa/x64/simd-bitwise-run.clif

@@ -1,7 +1,6 @@
 test run
 set enable_simd
-target x86_64 skylake
-feature "experimental_x64"
+target x86_64 machinst skylake
 
 function %bitselect_i8x16(i8x16, i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16, v2: i8x16):

cranelift/filetests/filetests/isa/x64/simd-comparison-legalize.clif

@@ -1,7 +1,6 @@
 test compile
 set enable_simd
-target x86_64 skylake
-feature "experimental_x64"
+target x86_64 machinst skylake
 
 function %icmp_ne_32x4(i32x4, i32x4) -> b32x4 {
 block0(v0: i32x4, v1: i32x4):

cranelift/filetests/filetests/isa/x64/simd-comparison-run.clif

@@ -1,7 +1,6 @@
 test run
 set enable_simd
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %icmp_eq_i8x16() -> b8 {
 block0:

cranelift/filetests/filetests/isa/x64/simd-conversion-run.clif

@@ -1,7 +1,6 @@
 test run
 set enable_simd
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %fcvt_from_sint() -> b1 {
 block0:

cranelift/filetests/filetests/isa/x64/simd-lane-access-compile.clif

@@ -1,7 +1,6 @@
 test compile
 set enable_simd
-target x86_64 has_ssse3 has_sse41
-feature "experimental_x64"
+target x86_64 machinst has_ssse3 has_sse41
 
 ;; shuffle
 

cranelift/filetests/filetests/isa/x64/simd-lane-access-run.clif

@@ -1,7 +1,6 @@
 test run
 set enable_simd
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 ;; shuffle
 

cranelift/filetests/filetests/isa/x64/simd-logical-compile.clif

@@ -1,7 +1,6 @@
 test compile
 set enable_simd
-target x86_64 skylake
-feature "experimental_x64"
+target x86_64 machinst skylake
 
 function %bnot_b32x4(b32x4) -> b32x4 {
 block0(v0: b32x4):

cranelift/filetests/filetests/isa/x64/simd-logical-run.clif

@@ -1,7 +1,6 @@
 test run
 set enable_simd
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %bnot() -> b32 {
 block0:

cranelift/filetests/filetests/isa/x64/struct-arg.clif

@@ -1,6 +1,5 @@
 test compile
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function u0:0(i64 sarg(64)) -> i8 system_v {
 block0(v0: i64):

cranelift/filetests/filetests/isa/x64/struct-ret.clif

@@ -1,6 +1,5 @@
 test compile
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %f0(i64 sret) {
 block0(v0: i64):

cranelift/filetests/filetests/isa/x64/tls_elf.clif

@@ -1,7 +1,6 @@
 test compile
 set tls_model=elf_gd
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function u0:0(i32) -> i64 {
 gv0 = symbol colocated tls u1:0

cranelift/filetests/filetests/isa/x64/uextend-elision.clif

@@ -1,6 +1,5 @@
 test compile
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 function %elide_uextend_add(i32, i32) -> i64 {
 block0(v0: i32, v1: i32):

cranelift/filetests/filetests/isa/x64/unused_jt_unreachable_block.clif

@@ -1,6 +1,5 @@
 test compile
-target x86_64
-feature "experimental_x64"
+target x86_64 machinst
 
 ;; From: https://github.com/bytecodealliance/wasmtime/issues/2670
 

cranelift/filetests/filetests/isa/x86/abcd.clif

@@ -1,5 +1,5 @@
 test regalloc
-target i686
+target i686 legacy
 
 ; %rdi can't be used in a movsbl instruction, so test that the register
 ; allocator can move it to a register that can be.

cranelift/filetests/filetests/isa/x86/abi-bool.clif

@@ -1,5 +1,5 @@
 test compile
-target x86_64 haswell
+target x86_64 legacy haswell
 
 function %foo(i64, i64, i64, i32) -> b1 system_v {
 block3(v0: i64, v1: i64, v2: i64, v3: i32):

cranelift/filetests/filetests/isa/x86/abi32.clif

@@ -1,6 +1,6 @@
 ; Test the legalization of function signatures.
 test legalizer
-target i686
+target i686 legacy
 
 ; regex: V=v\d+
 

cranelift/filetests/filetests/isa/x86/abi64.clif

@@ -1,6 +1,6 @@
 ; Test the legalization of function signatures.
 test legalizer
-target x86_64
+target x86_64 legacy
 
 ; regex: V=v\d+
 

cranelift/filetests/filetests/isa/x86/allones_funcaddrs32.clif

@@ -2,7 +2,7 @@
 test binemit
 set opt_level=speed_and_size
 set emit_all_ones_funcaddrs
-target i686 haswell
+target i686 legacy haswell
 
 ; The binary encodings can be verified with the command:
 ;

cranelift/filetests/filetests/isa/x86/allones_funcaddrs64.clif

@@ -2,7 +2,7 @@
 test binemit
 set opt_level=speed_and_size
 set emit_all_ones_funcaddrs
-target x86_64 haswell
+target x86_64 legacy haswell
 
 ; The binary encodings can be verified with the command:
 ;

cranelift/filetests/filetests/isa/x86/baldrdash-table-sig-reg.clif

@@ -1,6 +1,6 @@
 test compile
 set enable_probestack=false
-target i686
+target i686 legacy
 
 function u0:0(i32 vmctx) baldrdash_system_v {
     sig0 = (i32 vmctx, i32 sigid) baldrdash_system_v

cranelift/filetests/filetests/isa/x86/baseline_clz_ctz_popcount.clif

@@ -1,5 +1,5 @@
 test compile
-target x86_64 baseline
+target x86_64 legacy baseline
 
 
 ; clz/ctz on 64 bit operands

cranelift/filetests/filetests/isa/x86/baseline_clz_ctz_popcount_encoding.clif

@@ -1,6 +1,6 @@
 test binemit
 set opt_level=speed_and_size
-target x86_64 baseline
+target x86_64 legacy baseline
 
 ; The binary encodings can be verified with the command:
 ;

cranelift/filetests/filetests/isa/x86/binary32-float.clif

@@ -1,6 +1,6 @@
 ; Binary emission of 32-bit floating point code.
 test binemit
-target i686 haswell
+target i686 legacy haswell
 
 ; The binary encodings can be verified with the command:
 ;

cranelift/filetests/filetests/isa/x86/binary32.clif

@@ -1,7 +1,7 @@
 ; binary emission of x86-32 code.
 test binemit
 set opt_level=speed_and_size
-target i686 haswell
+target i686 legacy haswell
 
 ; The binary encodings can be verified with the command:
 ;

cranelift/filetests/filetests/isa/x86/binary64-float.clif

@@ -1,7 +1,7 @@
 ; Binary emission of 64-bit floating point code.
 test binemit
 set opt_level=speed_and_size
-target x86_64 haswell
+target x86_64 legacy haswell
 
 ; The binary encodings can be verified with the command:
 ;

cranelift/filetests/filetests/isa/x86/binary64-pic.clif

@@ -2,7 +2,7 @@
 test binemit
 set opt_level=speed_and_size
 set is_pic
-target x86_64 haswell
+target x86_64 legacy haswell
 
 ; The binary encodings can be verified with the command:
 ;

cranelift/filetests/filetests/isa/x86/binary64-run.clif

@@ -1,5 +1,5 @@
 test run
-target x86_64
+target x86_64 legacy
 
 ; this verifies that returning b64 immediates does not result in a segmentation fault, see https://github.com/bytecodealliance/cranelift/issues/911
 function %test_b64() -> b64 {

cranelift/filetests/filetests/isa/x86/binary64.clif

@@ -1,7 +1,7 @@
 ; binary emission of x86-64 code.
 test binemit
 set opt_level=speed_and_size
-target x86_64 haswell
+target x86_64 legacy haswell
 
 ; The binary encodings can be verified with the command:
 ;

cranelift/filetests/filetests/isa/x86/bitrev-i128-run.clif

@@ -1,5 +1,5 @@
 test run
-target x86_64
+target x86_64 legacy
 
 function %reverse_bits_zero() -> b1 {
 block0:

cranelift/filetests/filetests/isa/x86/bnot-b1.clif

@@ -1,7 +1,7 @@
 test binemit
 test run
 
-target x86_64
+target x86_64 legacy
 
 function u0:323() -> b1 {
 block0:

cranelift/filetests/filetests/isa/x86/br-i128-run.clif

@@ -1,5 +1,5 @@
 test run
-target x86_64
+target x86_64 legacy
 
 function %br_false() -> b1 {
 block0:

cranelift/filetests/filetests/isa/x86/br-i128.clif

@@ -1,5 +1,5 @@
 test compile
-target x86_64
+target x86_64 legacy
 
 function u0:0(i128) -> i8 fast {
 block0(v0: i128):

cranelift/filetests/filetests/isa/x86/brz-i8-run.clif

@@ -1,5 +1,5 @@
 test run
-target x86_64
+target x86_64 legacy
 
 function u0:0() -> b1 {
 block0:

cranelift/filetests/filetests/isa/x86/brz-i8.clif

@@ -1,5 +1,5 @@
 test compile
-target x86_64
+target x86_64 legacy
 
 function u0:0() -> b1 {
 block0:

cranelift/filetests/filetests/isa/x86/brz-x86_32-i64.clif

@@ -1,5 +1,5 @@
 test compile
-target i686
+target i686 legacy
 
 function u0:0(i32, i32) -> i32 {
 block0(v0: i32, v1: i32):

cranelift/filetests/filetests/isa/x86/extend-i128-run.clif

@@ -1,5 +1,5 @@
 test run
-target x86_64
+target x86_64 legacy
 
 function u0:0() -> b1 {
 block0:

cranelift/filetests/filetests/isa/x86/extend-i128.clif

@@ -1,5 +1,5 @@
 test compile
-target x86_64
+target x86_64 legacy
 
 function u0:0() -> b1 {
 block0:

cranelift/filetests/filetests/isa/x86/extend-i64-run.clif

@@ -1,5 +1,5 @@
 test run
-target i686
+target i686 legacy
 
 function u0:0() -> b1 {
 block0:

cranelift/filetests/filetests/isa/x86/extend-i64.clif

@@ -1,5 +1,5 @@
 test compile
-target i686
+target i686 legacy
 
 function u0:0() -> b1 {
 block0:

cranelift/filetests/filetests/isa/x86/floating-point-zero-constants-32bit.clif

@@ -1,6 +1,6 @@
 ; Check that floating-point and integer constants equal to zero are optimized correctly.
 test binemit
-target i686
+target i686 legacy
 
 function %foo() -> f32 fast {
 block0:

cranelift/filetests/filetests/isa/x86/floating-point-zero-constants.clif

@@ -1,6 +1,6 @@
 ; Check that floating-point constants equal to zero are optimized correctly.
 test binemit
-target x86_64
+target x86_64 legacy
 
 function %zero_const_32bit_no_rex() -> f32 fast {
 block0:

cranelift/filetests/filetests/isa/x86/i128-isplit-forward-jump.clif

@@ -1,5 +1,5 @@
 test compile
-target x86_64
+target x86_64 legacy
 
 function u0:0() -> i128 system_v {
 block0:

cranelift/filetests/filetests/isa/x86/i128.clif

@@ -1,5 +1,5 @@
 test compile
-target x86_64
+target x86_64 legacy
 
 function u0:0(i64, i64) -> i128 fast {
 block0(v0: i64, v1: i64):

cranelift/filetests/filetests/isa/x86/icmp-i128.clif

@@ -1,5 +1,5 @@
 test run
-target x86_64 haswell
+target x86_64 legacy haswell
 
 function %test_icmp_eq_i128() -> b1 {
 block0:

cranelift/filetests/filetests/isa/x86/imul-i128.clif

@@ -1,5 +1,5 @@
 test run
-target x86_64 haswell
+target x86_64 legacy haswell
 
 function %test_imul_i128() -> b1 {
 block0:

cranelift/filetests/filetests/isa/x86/ireduce-i16-to-i8.clif

@@ -1,5 +1,5 @@
 test compile
-target x86_64
+target x86_64 legacy
 
 function u0:0(i16) -> i8 fast {
 block0(v0: i16):

cranelift/filetests/filetests/isa/x86/isplit-not-legalized-twice.clif

@@ -1,5 +1,5 @@
 test compile
-target x86_64
+target x86_64 legacy
 
 function u0:0(i64, i64) -> i128 system_v {
 block0(v0: i64, v1: i64):

cranelift/filetests/filetests/isa/x86/isub_imm-i8.clif

@@ -1,6 +1,6 @@
 test compile
 set opt_level=speed_and_size
-target x86_64
+target x86_64 legacy
 
 function u0:0(i8) -> i8 fast {
 block0(v0: i8):

cranelift/filetests/filetests/isa/x86/jump_i128_param_unused.clif

@@ -1,5 +1,5 @@
 test compile
-target x86_64
+target x86_64 legacy
 
 function u0:0(i128) system_v {
 block0(v0: i128):

cranelift/filetests/filetests/isa/x86/legalize-bint-i8.clif

@@ -1,6 +1,6 @@
 test compile
 
-target x86_64
+target x86_64 legacy
 
 function u0:0() -> i8 fast {
 block0:

cranelift/filetests/filetests/isa/x86/legalize-bnot.clif

@@ -1,6 +1,6 @@
 test compile
 
-target x86_64
+target x86_64 legacy
 
 function u0:51(i64, i64) system_v {
     ss0 = explicit_slot 0

cranelift/filetests/filetests/isa/x86/legalize-br-icmp.clif

@@ -1,6 +1,6 @@
 test legalizer
 
-target x86_64
+target x86_64 legacy
 
 function %br_icmp(i64) fast {
 block0(v0: i64):

cranelift/filetests/filetests/isa/x86/legalize-br-table.clif

@@ -1,6 +1,6 @@
 test compile
 set opt_level=speed_and_size
-target x86_64
+target x86_64 legacy
 ; regex: V=v\d+
 ; regex: BB=block\d+
 

cranelift/filetests/filetests/isa/x86/legalize-byte-ops-i8.clif

@@ -1,5 +1,5 @@
 test compile
-target x86_64
+target x86_64 legacy
 
 ; regex: V=v\d+
 

cranelift/filetests/filetests/isa/x86/legalize-call.clif

@@ -1,7 +1,7 @@
 ; Test legalization of a non-colocated call in 64-bit non-PIC mode.
 test legalizer
 set opt_level=speed_and_size
-target x86_64 haswell
+target x86_64 legacy haswell
 
 function %call() {
     fn0 = %foo()

cranelift/filetests/filetests/isa/x86/legalize-clz-ctz-i8.clif

@@ -1,5 +1,5 @@
 test compile
-target x86_64
+target x86_64 legacy
 
 ; regex: V=v\d+
 

cranelift/filetests/filetests/isa/x86/legalize-custom.clif

@@ -1,7 +1,7 @@
 ; Test the custom legalizations.
 test legalizer
-target i686
-target x86_64
+target i686 legacy
+target x86_64 legacy
 
 ; regex: V=v\d+
 ; regex: BB=block\d+

cranelift/filetests/filetests/isa/x86/legalize-div-traps.clif

@@ -2,7 +2,7 @@
 test legalizer
 ; See also legalize-div.clif.
 set avoid_div_traps=1
-target x86_64
+target x86_64 legacy
 
 ; regex: V=v\d+
 ; regex: BB=block\d+

cranelift/filetests/filetests/isa/x86/legalize-div.clif

@@ -2,7 +2,7 @@
 test legalizer
 ; See also legalize-div-traps.clif.
 set avoid_div_traps=0
-target x86_64
+target x86_64 legacy
 
 ; regex: V=v\d+
 ; regex: BB=block\d+

cranelift/filetests/filetests/isa/x86/legalize-f64const-x64.clif

@@ -1,6 +1,6 @@
 ; Test the legalization of f64const.
 test legalizer
-target x86_64
+target x86_64 legacy
 
 ; regex: V=v\d+
 

cranelift/filetests/filetests/isa/x86/legalize-fcvt_from_usint-i16.clif

@@ -1,5 +1,5 @@
 test compile
-target x86_64
+target x86_64 legacy
 
 function u0:0(i16) -> f64 fast {
 block0(v0: i16):

cranelift/filetests/filetests/isa/x86/legalize-heaps.clif

@@ -1,6 +1,6 @@
 test legalizer
 set enable_heap_access_spectre_mitigation=false
-target x86_64
+target x86_64 legacy
 
 ; Test legalization for various forms of heap addresses.
 ; regex: BB=block\d+

cranelift/filetests/filetests/isa/x86/legalize-i128.clif

@@ -1,6 +1,6 @@
 ; Test the legalization of i128 instructions on x86_64.
 test legalizer
-target x86_64 haswell
+target x86_64 legacy haswell
 
 ; regex: V=v\d+
 

cranelift/filetests/filetests/isa/x86/legalize-i64.clif

@@ -1,6 +1,6 @@
 ; Test the legalization of i64 instructions on x86_32.
 test legalizer
-target i686 haswell
+target i686 legacy haswell
 
 ; regex: V=v\d+
 

cranelift/filetests/filetests/isa/x86/legalize-icmp-i8.clif

@@ -1,5 +1,5 @@
 test compile
-target x86_64
+target x86_64 legacy
 
 ; regex: V=v\d+
 

cranelift/filetests/filetests/isa/x86/legalize-iconst-i8.clif

@@ -1,6 +1,6 @@
 test compile
 
-target x86_64
+target x86_64 legacy
 
 function u0:0(i64) system_v {
     ss0 = explicit_slot 0

cranelift/filetests/filetests/isa/x86/legalize-imul-i8.clif

@@ -1,6 +1,6 @@
 test compile
 
-target x86_64
+target x86_64 legacy
 
 function u0:0(i64, i8, i8) system_v {