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fix rotl.i16 with i128 shift value. (#5611)

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* fix issue 5523.

* fix.

* add missing issue file.

* fix issue.

* fix duplicate shamt_128.

* issue 5523 add test target,and fix some wrong comment.

* fix output file.

* enable llvm_abi_extensions for regression test file.
This commit is contained in:
yuyang
2023-02-01 11:44:13 +08:00
committed by GitHub
parent 268f6bfc1d
commit cb3b6c621f
5 changed files with 133 additions and 103 deletions
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5
cranelift/codegen/src/isa/riscv64/lower/isle.rs
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@@ -253,19 +253,20 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Riscv64Backend> {
//
fn gen_shamt(&mut self, ty: Type, shamt: Reg) -> ValueRegs {
let ty_bits = if ty.bits() > 64 { 64 } else { ty.bits() };
let shamt = {
let tmp = self.temp_writable_reg(I64);
self.emit(&MInst::AluRRImm12 {
alu_op: AluOPRRI::Andi,
rd: tmp,
rs: shamt,
imm12: Imm12::from_bits((ty.bits() - 1) as i16),
imm12: Imm12::from_bits((ty_bits - 1) as i16),
});
tmp.to_reg()
};
let len_sub_shamt = {
let tmp = self.temp_writable_reg(I64);
self.emit(&MInst::load_imm12(tmp, Imm12::from_bits(ty.bits() as i16)));
self.emit(&MInst::load_imm12(tmp, Imm12::from_bits(ty_bits as i16)));
let len_sub_shamt = self.temp_writable_reg(I64);
self.emit(&MInst::AluRRR {
alu_op: AluOPRRR::Sub,