Translate existing WASM SIMD operations to CLIF
This commit is contained in:
Andrew Brown
@@ -922,30 +922,46 @@ pub fn translate_operator<FE: FuncEnvironment + ?Sized>(
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| Operator::TableSize { .. } => {
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wasm_unsupported!("proposed bulk memory operator {:?}", op);
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}
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Operator::V128Const { value } => {
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let constant = builder.func.dfg.constants.insert(value.bytes().to_vec());
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state.push1(builder.ins().vconst(I32X4, constant)) // TODO need to decide what to do about I32X4 here; the WASM spec has V128
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}
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Operator::I8x16Splat
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| Operator::I16x8Splat
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| Operator::I32x4Splat
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| Operator::I64x2Splat
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| Operator::F32x4Splat
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| Operator::F64x2Splat => {
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let value_to_splat = state.pop1();
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let ty = type_of(op);
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state.push1(builder.ins().splat(ty, value_to_splat))
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}
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Operator::I32x4ExtractLane { lane }
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| Operator::I64x2ExtractLane { lane }
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| Operator::F32x4ExtractLane { lane }
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| Operator::F64x2ExtractLane { lane } => {
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let vector = state.pop1();
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state.push1(builder.ins().extractlane(vector, lane.clone()))
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}
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Operator::I8x16ReplaceLane { lane }
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| Operator::I16x8ReplaceLane { lane }
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| Operator::I32x4ReplaceLane { lane }
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| Operator::I64x2ReplaceLane { lane }
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| Operator::F32x4ReplaceLane { lane }
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| Operator::F64x2ReplaceLane { lane } => {
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let (vector, replacement_value) = state.pop2();
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let replaced_vector = builder
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.ins()
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.insertlane(vector, lane.clone(), replacement_value);
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state.push1(replaced_vector)
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}
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Operator::V128Load { .. }
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| Operator::V128Store { .. }
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| Operator::V128Const { .. }
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| Operator::V8x16Shuffle { .. }
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| Operator::I8x16Splat
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| Operator::I8x16ExtractLaneS { .. }
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| Operator::I8x16ExtractLaneU { .. }
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| Operator::I8x16ReplaceLane { .. }
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| Operator::I16x8Splat
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| Operator::I16x8ExtractLaneS { .. }
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| Operator::I16x8ExtractLaneU { .. }
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| Operator::I16x8ReplaceLane { .. }
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| Operator::I32x4Splat
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| Operator::I32x4ExtractLane { .. }
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| Operator::I32x4ReplaceLane { .. }
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| Operator::I64x2Splat
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| Operator::I64x2ExtractLane { .. }
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| Operator::I64x2ReplaceLane { .. }
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| Operator::F32x4Splat
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| Operator::F32x4ExtractLane { .. }
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| Operator::F32x4ReplaceLane { .. }
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| Operator::F64x2Splat
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| Operator::F64x2ExtractLane { .. }
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| Operator::F64x2ReplaceLane { .. }
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| Operator::V8x16Shuffle { .. }
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| Operator::I8x16Eq
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| Operator::I8x16Ne
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| Operator::I8x16LtS
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@@ -1291,3 +1307,160 @@ fn translate_br_if_args(
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let inputs = state.peekn(return_count);
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(br_destination, inputs)
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}
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/// Determine the returned value type of a WebAssembly operator
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fn type_of(operator: &Operator) -> Type {
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match operator {
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Operator::V128Load { .. }
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| Operator::V128Store { .. }
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| Operator::V128Const { .. }
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| Operator::V128Not
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| Operator::V128And
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| Operator::V128Or
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| Operator::V128Xor
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| Operator::V128Bitselect => I32X4, // TODO this is used as a default until we determine what to do about the spec's V128
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Operator::V8x16Shuffle { .. }
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| Operator::I8x16Splat
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| Operator::I8x16ExtractLaneS { .. }
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| Operator::I8x16ExtractLaneU { .. }
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| Operator::I8x16ReplaceLane { .. }
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| Operator::I8x16Eq
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| Operator::I8x16Ne
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| Operator::I8x16LtS
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| Operator::I8x16LtU
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| Operator::I8x16GtS
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| Operator::I8x16GtU
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| Operator::I8x16LeS
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| Operator::I8x16LeU
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| Operator::I8x16GeS
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| Operator::I8x16GeU
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| Operator::I8x16Neg
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| Operator::I8x16AnyTrue
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| Operator::I8x16AllTrue
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| Operator::I8x16Shl
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| Operator::I8x16ShrS
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| Operator::I8x16ShrU
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| Operator::I8x16Add
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| Operator::I8x16AddSaturateS
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| Operator::I8x16AddSaturateU
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| Operator::I8x16Sub
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| Operator::I8x16SubSaturateS
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| Operator::I8x16SubSaturateU
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| Operator::I8x16Mul => I8X16,
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Operator::I16x8Splat
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| Operator::I16x8ExtractLaneS { .. }
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| Operator::I16x8ExtractLaneU { .. }
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| Operator::I16x8ReplaceLane { .. }
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| Operator::I16x8Eq
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| Operator::I16x8Ne
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| Operator::I16x8LtS
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| Operator::I16x8LtU
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| Operator::I16x8GtS
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| Operator::I16x8GtU
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| Operator::I16x8LeS
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| Operator::I16x8LeU
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| Operator::I16x8GeS
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| Operator::I16x8GeU
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| Operator::I16x8Neg
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| Operator::I16x8AnyTrue
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| Operator::I16x8AllTrue
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| Operator::I16x8Shl
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| Operator::I16x8ShrS
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| Operator::I16x8ShrU
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| Operator::I16x8Add
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| Operator::I16x8AddSaturateS
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| Operator::I16x8AddSaturateU
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| Operator::I16x8Sub
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| Operator::I16x8SubSaturateS
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| Operator::I16x8SubSaturateU
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| Operator::I16x8Mul => I16X8,
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Operator::I32x4Splat
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| Operator::I32x4ExtractLane { .. }
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| Operator::I32x4ReplaceLane { .. }
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| Operator::I32x4Eq
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| Operator::I32x4Ne
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| Operator::I32x4LtS
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| Operator::I32x4LtU
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| Operator::I32x4GtS
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| Operator::I32x4GtU
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| Operator::I32x4LeS
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| Operator::I32x4LeU
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| Operator::I32x4GeS
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| Operator::I32x4GeU
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| Operator::I32x4Neg
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| Operator::I32x4AnyTrue
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| Operator::I32x4AllTrue
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| Operator::I32x4Shl
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| Operator::I32x4ShrS
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| Operator::I32x4ShrU
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| Operator::I32x4Add
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| Operator::I32x4Sub
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| Operator::I32x4Mul
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| Operator::F32x4ConvertSI32x4
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| Operator::F32x4ConvertUI32x4 => I32X4,
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Operator::I64x2Splat
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| Operator::I64x2ExtractLane { .. }
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| Operator::I64x2ReplaceLane { .. }
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| Operator::I64x2Neg
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| Operator::I64x2AnyTrue
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| Operator::I64x2AllTrue
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| Operator::I64x2Shl
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| Operator::I64x2ShrS
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| Operator::I64x2ShrU
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| Operator::I64x2Add
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| Operator::I64x2Sub
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| Operator::F64x2ConvertSI64x2
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| Operator::F64x2ConvertUI64x2 => I64X2,
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Operator::F32x4Splat
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| Operator::F32x4ExtractLane { .. }
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| Operator::F32x4ReplaceLane { .. }
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| Operator::F32x4Eq
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| Operator::F32x4Ne
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| Operator::F32x4Lt
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| Operator::F32x4Gt
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| Operator::F32x4Le
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| Operator::F32x4Ge
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| Operator::F32x4Abs
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| Operator::F32x4Neg
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| Operator::F32x4Sqrt
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| Operator::F32x4Add
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| Operator::F32x4Sub
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| Operator::F32x4Mul
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| Operator::F32x4Div
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| Operator::F32x4Min
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| Operator::F32x4Max
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| Operator::I32x4TruncSF32x4Sat
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| Operator::I32x4TruncUF32x4Sat => F32X4,
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Operator::F64x2Splat
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| Operator::F64x2ExtractLane { .. }
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| Operator::F64x2ReplaceLane { .. }
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| Operator::F64x2Eq
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| Operator::F64x2Ne
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| Operator::F64x2Lt
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| Operator::F64x2Gt
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| Operator::F64x2Le
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| Operator::F64x2Ge
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| Operator::F64x2Abs
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| Operator::F64x2Neg
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| Operator::F64x2Sqrt
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| Operator::F64x2Add
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| Operator::F64x2Sub
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| Operator::F64x2Mul
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| Operator::F64x2Div
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| Operator::F64x2Min
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| Operator::F64x2Max
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| Operator::I64x2TruncSF64x2Sat
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| Operator::I64x2TruncUF64x2Sat => F64X2,
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_ => unimplemented!(
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"Currently only the SIMD instructions are translated to their return type: {:?}",
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operator
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),
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}
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}
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