Add RISC-V regmove encodings.

lib/cretonne/meta/isa/riscv/encodings.py

@@ -8,7 +8,7 @@ from .defs import RV32, RV64
 from .recipes import OPIMM, OPIMM32, OP, OP32, LUI, BRANCH, JALR, JAL
 from .recipes import LOAD, STORE
 from .recipes import R, Rshamt, Ricmp, I, Iz, Iicmp, Iret, Icall, Icopy
-from .recipes import U, UJ, UJcall, SB, SBzero, GPsp, GPfi
+from .recipes import U, UJ, UJcall, SB, SBzero, GPsp, GPfi, Irmov
 from .settings import use_m
 from cdsl.ast import Var
 
@@ -135,3 +135,7 @@ RV64.enc(base.fill.i64, GPfi, LOAD(0b011))
 RV32.enc(base.copy.i32, Icopy, OPIMM(0b000))
 RV64.enc(base.copy.i64, Icopy, OPIMM(0b000))
 RV64.enc(base.copy.i32, Icopy, OPIMM32(0b000))
+
+RV32.enc(base.regmove.i32, Irmov, OPIMM(0b000))
+RV64.enc(base.regmove.i64, Irmov, OPIMM(0b000))
+RV64.enc(base.regmove.i32, Irmov, OPIMM32(0b000))

lib/cretonne/meta/isa/riscv/recipes.py

@@ -14,7 +14,7 @@ from cdsl.predicates import IsSignedInt
 from cdsl.registers import Stack
 from base.formats import Binary, BinaryImm, MultiAry, IntCompare, IntCompareImm
 from base.formats import Unary, UnaryImm, BranchIcmp, Branch, Jump
-from base.formats import Call, IndirectCall
+from base.formats import Call, IndirectCall, RegMove
 from .registers import GPR
 
 # The low 7 bits of a RISC-V instruction is the base opcode. All 32-bit
@@ -156,6 +156,11 @@ Icopy = EncRecipe(
         'Icopy', Unary, size=4, ins=GPR, outs=GPR,
         emit='put_i(bits, in_reg0, 0, out_reg0, sink);')
 
+# Same for a GPR regmove.
+Irmov = EncRecipe(
+        'Irmov', RegMove, size=4, ins=GPR, outs=(),
+        emit='put_i(bits, src, 0, dst, sink);')
+
 # U-type instructions have a 20-bit immediate that targets bits 12-31.
 U = EncRecipe(
         'U', UnaryImm, size=4, ins=(), outs=GPR,