From ca4582ae8231b139f6bc2bdf32fe0f1d3d0d7b99 Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Mon, 19 Mar 2018 09:13:47 -0700 Subject: [PATCH] Rename the recipes for x86 spill/fill instructions. Both "sp" and "fi" have multiple meanings in this context, so use slightly longer but less ambiguous names. --- lib/cretonne/meta/isa/intel/encodings.py | 32 +++++++++---------- lib/cretonne/meta/isa/intel/recipes.py | 40 ++++++++++++++---------- 2 files changed, 40 insertions(+), 32 deletions(-) diff --git a/lib/cretonne/meta/isa/intel/encodings.py b/lib/cretonne/meta/isa/intel/encodings.py index 995149794a..489e61be9f 100644 --- a/lib/cretonne/meta/isa/intel/encodings.py +++ b/lib/cretonne/meta/isa/intel/encodings.py @@ -205,14 +205,14 @@ for recipe in [r.st_abcd, r.stDisp8_abcd, r.stDisp32_abcd]: enc_both(base.istore8.i32.any, recipe, 0x88) enc_x86_64(base.istore8.i64.any, recipe, 0x88) -enc_i32_i64(base.spill, r.spSib32, 0x89) -enc_i32_i64(base.regspill, r.rsp32, 0x89) +enc_i32_i64(base.spill, r.spillSib32, 0x89) +enc_i32_i64(base.regspill, r.regspill32, 0x89) # Use a 32-bit write for spilling `b1` to avoid constraining the permitted # registers. # See MIN_SPILL_SLOT_SIZE which makes this safe. -enc_both(base.spill.b1, r.spSib32, 0x89) -enc_both(base.regspill.b1, r.rsp32, 0x89) +enc_both(base.spill.b1, r.spillSib32, 0x89) +enc_both(base.regspill.b1, r.regspill32, 0x89) for recipe in [r.ld, r.ldDisp8, r.ldDisp32]: enc_i32_i64_ld_st(base.load, True, recipe, 0x8b) @@ -223,12 +223,12 @@ for recipe in [r.ld, r.ldDisp8, r.ldDisp32]: enc_i32_i64_ld_st(base.uload8, True, recipe, 0x0f, 0xb6) enc_i32_i64_ld_st(base.sload8, True, recipe, 0x0f, 0xbe) -enc_i32_i64(base.fill, r.fiSib32, 0x8b) -enc_i32_i64(base.regfill, r.rfi32, 0x8b) +enc_i32_i64(base.fill, r.fillSib32, 0x8b) +enc_i32_i64(base.regfill, r.regfill32, 0x8b) # Load 32 bits from `b1` spill slots. See `spill.b1` above. -enc_both(base.fill.b1, r.fiSib32, 0x8b) -enc_both(base.regfill.b1, r.rfi32, 0x8b) +enc_both(base.fill.b1, r.fillSib32, 0x8b) +enc_both(base.regfill.b1, r.regfill32, 0x8b) # Push and Pop X86_32.enc(x86.push.i32, *r.pushq(0x50)) @@ -267,15 +267,15 @@ enc_both(base.store.f64.any, r.fst, 0x66, 0x0f, 0xd6) enc_both(base.store.f64.any, r.fstDisp8, 0x66, 0x0f, 0xd6) enc_both(base.store.f64.any, r.fstDisp32, 0x66, 0x0f, 0xd6) -enc_both(base.fill.f32, r.ffiSib32, 0x66, 0x0f, 0x6e) -enc_both(base.regfill.f32, r.frfi32, 0x66, 0x0f, 0x6e) -enc_both(base.fill.f64, r.ffiSib32, 0xf3, 0x0f, 0x7e) -enc_both(base.regfill.f64, r.frfi32, 0xf3, 0x0f, 0x7e) +enc_both(base.fill.f32, r.ffillSib32, 0x66, 0x0f, 0x6e) +enc_both(base.regfill.f32, r.fregfill32, 0x66, 0x0f, 0x6e) +enc_both(base.fill.f64, r.ffillSib32, 0xf3, 0x0f, 0x7e) +enc_both(base.regfill.f64, r.fregfill32, 0xf3, 0x0f, 0x7e) -enc_both(base.spill.f32, r.fspSib32, 0x66, 0x0f, 0x7e) -enc_both(base.regspill.f32, r.frsp32, 0x66, 0x0f, 0x7e) -enc_both(base.spill.f64, r.fspSib32, 0x66, 0x0f, 0xd6) -enc_both(base.regspill.f64, r.frsp32, 0x66, 0x0f, 0xd6) +enc_both(base.spill.f32, r.fspillSib32, 0x66, 0x0f, 0x7e) +enc_both(base.regspill.f32, r.fregspill32, 0x66, 0x0f, 0x7e) +enc_both(base.spill.f64, r.fspillSib32, 0x66, 0x0f, 0xd6) +enc_both(base.regspill.f64, r.fregspill32, 0x66, 0x0f, 0xd6) # # Function addresses. diff --git a/lib/cretonne/meta/isa/intel/recipes.py b/lib/cretonne/meta/isa/intel/recipes.py index 9d03d02053..9d015a25bb 100644 --- a/lib/cretonne/meta/isa/intel/recipes.py +++ b/lib/cretonne/meta/isa/intel/recipes.py @@ -756,8 +756,8 @@ fstDisp32 = TailRecipe( ''') # Unary spill with SIB and 32-bit displacement. -spSib32 = TailRecipe( - 'spSib32', Unary, size=6, ins=GPR, outs=StackGPR32, +spillSib32 = TailRecipe( + 'spillSib32', Unary, size=6, ins=GPR, outs=StackGPR32, clobbers_flags=False, emit=''' let base = stk_base(out_stk0.base); @@ -766,8 +766,10 @@ spSib32 = TailRecipe( sib_noindex(base, sink); sink.put4(out_stk0.offset as u32); ''') -fspSib32 = TailRecipe( - 'fspSib32', Unary, size=6, ins=FPR, outs=StackFPR32, + +# Like spillSib32, but targeting an FPR rather than a GPR. +fspillSib32 = TailRecipe( + 'fspillSib32', Unary, size=6, ins=FPR, outs=StackFPR32, clobbers_flags=False, emit=''' let base = stk_base(out_stk0.base); @@ -778,8 +780,8 @@ fspSib32 = TailRecipe( ''') # Regspill using RSP-relative addressing. -rsp32 = TailRecipe( - 'rsp32', RegSpill, size=6, ins=GPR, outs=(), +regspill32 = TailRecipe( + 'regspill32', RegSpill, size=6, ins=GPR, outs=(), clobbers_flags=False, emit=''' let dst = StackRef::sp(dst, &func.stack_slots); @@ -789,8 +791,10 @@ rsp32 = TailRecipe( sib_noindex(base, sink); sink.put4(dst.offset as u32); ''') -frsp32 = TailRecipe( - 'frsp32', RegSpill, size=6, ins=FPR, outs=(), + +# Like regspill32, but targeting an FPR rather than a GPR. +fregspill32 = TailRecipe( + 'fregspill32', RegSpill, size=6, ins=FPR, outs=(), clobbers_flags=False, emit=''' let dst = StackRef::sp(dst, &func.stack_slots); @@ -874,8 +878,8 @@ fldDisp32 = TailRecipe( ''') # Unary fill with SIB and 32-bit displacement. -fiSib32 = TailRecipe( - 'fiSib32', Unary, size=6, ins=StackGPR32, outs=GPR, +fillSib32 = TailRecipe( + 'fillSib32', Unary, size=6, ins=StackGPR32, outs=GPR, clobbers_flags=False, emit=''' let base = stk_base(in_stk0.base); @@ -884,8 +888,10 @@ fiSib32 = TailRecipe( sib_noindex(base, sink); sink.put4(in_stk0.offset as u32); ''') -ffiSib32 = TailRecipe( - 'ffiSib32', Unary, size=6, ins=StackFPR32, outs=FPR, + +# Like fillSib32, but targeting an FPR rather than a GPR. +ffillSib32 = TailRecipe( + 'ffillSib32', Unary, size=6, ins=StackFPR32, outs=FPR, clobbers_flags=False, emit=''' let base = stk_base(in_stk0.base); @@ -896,8 +902,8 @@ ffiSib32 = TailRecipe( ''') # Regfill with RSP-relative 32-bit displacement. -rfi32 = TailRecipe( - 'rfi32', RegFill, size=6, ins=StackGPR32, outs=(), +regfill32 = TailRecipe( + 'regfill32', RegFill, size=6, ins=StackGPR32, outs=(), clobbers_flags=False, emit=''' let src = StackRef::sp(src, &func.stack_slots); @@ -907,8 +913,10 @@ rfi32 = TailRecipe( sib_noindex(base, sink); sink.put4(src.offset as u32); ''') -frfi32 = TailRecipe( - 'frfi32', RegFill, size=6, ins=StackFPR32, outs=(), + +# Like regfill32, but targeting an FPR rather than a GPR. +fregfill32 = TailRecipe( + 'fregfill32', RegFill, size=6, ins=StackFPR32, outs=(), clobbers_flags=False, emit=''' let src = StackRef::sp(src, &func.stack_slots);