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Add subtract and logical instruction encodings to Intel-32.

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Also add versions with 8-bit and 32-bit immediate operands.
This commit is contained in:
Jakob Stoklund Olesen
2017-05-12 10:35:18 -07:00
parent 3aaa8b2f91
commit c998df6274
5 changed files with 117 additions and 10 deletions
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24
lib/cretonne/src/isa/intel/binemit.rs
View File

@@ -53,3 +53,27 @@ fn recipe_op1rc<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut C
panic!("Expected Binary format: {:?}", func.dfg[inst]);
}
}
fn recipe_op1rib<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
if let InstructionData::BinaryImm { arg, imm, .. } = func.dfg[inst] {
let bits = func.encodings[inst].bits();
put_op1(bits, sink);
modrm_r_bits(func.locations[arg].unwrap_reg(), bits, sink);
let imm: i64 = imm.into();
sink.put1(imm as u8);
} else {
panic!("Expected BinaryImm format: {:?}", func.dfg[inst]);
}
}
fn recipe_op1rid<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
if let InstructionData::BinaryImm { arg, imm, .. } = func.dfg[inst] {
let bits = func.encodings[inst].bits();
put_op1(bits, sink);
modrm_r_bits(func.locations[arg].unwrap_reg(), bits, sink);
let imm: i64 = imm.into();
sink.put4(imm as u32);
} else {
panic!("Expected BinaryImm format: {:?}", func.dfg[inst]);
}
}

3
lib/cretonne/src/isa/intel/enc_tables.rs
View File

@@ -1,11 +1,12 @@
//! Encoding tables for Intel ISAs.
use ir::{Opcode, InstructionData};
use ir::types;
use ir::{Opcode, InstructionData};
use isa::EncInfo;
use isa::constraints::*;
use isa::enc_tables::{Level1Entry, Level2Entry};
use isa::encoding::RecipeSizing;
use predicates;
use super::registers::*;
include!(concat!(env!("OUT_DIR"), "/encoding-intel.rs"));